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Rimfaxe
vme_core
Commits
fcc36f75
Commit
fcc36f75
authored
Apr 17, 2020
by
Michael Munch
Browse files
Explicit timeout
parent
f70ddcf0
Pipeline
#19349
failed with stage
in 40 seconds
Changes
1
Pipelines
1
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Inline
Side-by-side
src/vme_data_bus.vhd
View file @
fcc36f75
...
...
@@ -148,7 +148,7 @@ entity vme_data_bus is
-- This is asserted when not IDLE.
signal
busy
:
out
std_logic
:
=
'0'
;
-- Latched from last VME read operation.
-- This is valid when int_data_strobe is high.
signal
int_data_o
:
out
vme_vec_64_t
;
...
...
@@ -180,7 +180,8 @@ entity vme_data_bus is
signal
int_blt_decided
:
in
std_logic
;
signal
int_blt_continue
:
in
std_logic
signal
int_blt_continue
:
in
std_logic
;
signal
int_timeout_n
:
in
std_logic
;
);
end
entity
;
...
...
@@ -471,10 +472,14 @@ begin
-- [30 ns]
--
-- Munk: Thus we can only catch BERR* here.
if
(
vme_berr_n_i
=
'0'
)
then
if
(
vme_berr_n_i
&
int_timeout_n
/=
"11"
)
then
vme_ds_n_o
<=
"11"
;
vme_as_n_o
<=
'1'
;
int_err_code
<=
c_ERR_BERR
;
vme_as_n_o
<=
'1'
;
if
(
int_timeout_n
=
'0'
)
then
int_err_code
<=
c_ERR_TIMEOUT
;
else
int_err_code
<=
c_ERR_BERR
;
end
if
;
busy
<=
'0'
;
state
<=
IDLE
;
...
...
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