Hide PSL default clock

src/vme_bus_arb.sby

@@ -7,7 +7,7 @@ smtbmc z3
 
 [script]
 ghdl -fpsl --std=08 -gformal=true vme_pkg.vhd vme_bus_arb.vhd -e vme_bus_arb
-prep -top vme_bus_arb
+prep -top vme_bus_arb_10_1
 
 [files]
 vme_bus_arb.vhd

src/vme_bus_arb.vhd

@@ -172,7 +172,7 @@ begin
       end if;
     end process;
 
-    default clock is rising_edge(clk);
+    -- psl default clock is rising_edge(clk);
 
     stay_in_idle_until_br_received:    
     assert always (state = IDLE and vme_br_n_i = "1111")

src/vme_cli_arb.sby

@@ -7,7 +7,7 @@ smtbmc z3
 
 [script]
 ghdl -fpsl --std=08 -gformal=true vme_pkg.vhd vme_cli_arb.vhd -e vme_cli_arb
-prep -top vme_cli_arb
+prep -top vme_cli_arb_1
 
 [files]
 vme_cli_arb.vhd

src/vme_cli_arb.vhd

@@ -259,7 +259,7 @@ begin
     end process;
     
     
-    default clock is rising_edge(clk);
+    -- psl default clock is rising_edge(clk);
 
     -- Two clients may not be active at the same time
     not_two_live:       assert always not (live_1 and live_2);

src/vme_data_bus.sby

@@ -7,7 +7,7 @@ smtbmc z3
 
 [script]
 ghdl -fpsl --std=08 -gformal=true vme_pkg.vhd vme_data_bus.vhd formal_vme_bus.vhd -e vme_data_bus
-prep -top vme_data_bus
+prep -top vme_data_bus_10_1
 
 [files]
 vme_data_bus.vhd

src/vme_data_bus.vhd

@@ -703,7 +703,7 @@ begin
       end if;
     end process;
 
-    default clock is rising_edge(clk);
+    -- psl default clock is rising_edge(clk);
     restrict {{vme_iack_n_i = '1' and vme_berr_n_i = '1'}[+]};
 
     -- Check that client input is latched