Commit f70ddcf0 authored by Michael Munch's avatar Michael Munch
Browse files

Added VME watchdog

parent 2555760c
Pipeline #19335 failed with stage
in 39 seconds
library ieee;
use ieee.std_logic_1164.all;
use work.vme_pkg.all;
entity vme_watchdog is
port (
signal clk : in std_logic;
signal vme_as_n_i : in std_logic;
signal vme_berr_n_o : out std_logic := '0';
signal vme_berr_n_dir : out std_logic := c_PIN_IN
);
end entity;
architecture rtl of vme_watchdog is
constant CNT_MAX : integer := 255;
signal cnt : integer range 0 to 255 := CNT_MAX;
begin
process (clk)
begin
if (rising_edge(clk)) then
if vme_as_n_i = '0' then
if cnt = 0 then
vme_berr_n_o <= '0';
vme_berr_n_dir <= c_PIN_OUT;
else
cnt <= cnt - 1;
end if;
else
vme_berr_n_o <= '1';
vme_berr_n_dir <= c_PIN_IN;
cnt <= CNT_MAX;
end if;
end if;
end process;
end architecture;
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment