Commit c7387e20 authored by Michael Munch's avatar Michael Munch
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Merge branch 'retzero'

parents 88f50c26 9118020e
Pipeline #48782 failed with stage
in 16 seconds
...@@ -27,6 +27,7 @@ entity vme_cli_arb is ...@@ -27,6 +27,7 @@ entity vme_cli_arb is
signal p1_int_data_strobe : out std_logic := c_DATA_CLEAR; signal p1_int_data_strobe : out std_logic := c_DATA_CLEAR;
signal p1_int_go_consumed_strobe : out std_logic := '0'; signal p1_int_go_consumed_strobe : out std_logic := '0';
signal p1_int_blt_decision : out std_logic := '0'; signal p1_int_blt_decision : out std_logic := '0';
signal p1_int_blt_decided_consumed : out std_logic := '0';
signal p1_int_err_code : out err_vec_t := C_ERR_OK; signal p1_int_err_code : out err_vec_t := C_ERR_OK;
signal p1_int_addr : in vme_addr_t; signal p1_int_addr : in vme_addr_t;
...@@ -39,6 +40,7 @@ entity vme_cli_arb is ...@@ -39,6 +40,7 @@ entity vme_cli_arb is
signal p1_int_blt_continue : in std_logic; signal p1_int_blt_continue : in std_logic;
signal p1_int_berr_ok : in std_logic; signal p1_int_berr_ok : in std_logic;
signal p1_int_retzero : in std_logic;
-- Signals to/from the second client. -- Signals to/from the second client.
...@@ -48,6 +50,7 @@ entity vme_cli_arb is ...@@ -48,6 +50,7 @@ entity vme_cli_arb is
signal p2_int_data_strobe : out std_logic := c_DATA_CLEAR; signal p2_int_data_strobe : out std_logic := c_DATA_CLEAR;
signal p2_int_go_consumed_strobe : out std_logic := '0'; signal p2_int_go_consumed_strobe : out std_logic := '0';
signal p2_int_blt_decision : out std_logic := '0'; signal p2_int_blt_decision : out std_logic := '0';
signal p2_int_blt_decided_consumed : out std_logic := '0';
signal p2_int_err_code : out err_vec_t := C_ERR_OK; signal p2_int_err_code : out err_vec_t := C_ERR_OK;
signal p2_int_addr : in vme_addr_t; signal p2_int_addr : in vme_addr_t;
...@@ -60,6 +63,7 @@ entity vme_cli_arb is ...@@ -60,6 +63,7 @@ entity vme_cli_arb is
signal p2_int_blt_continue : in std_logic; signal p2_int_blt_continue : in std_logic;
signal p2_int_berr_ok : in std_logic; signal p2_int_berr_ok : in std_logic;
signal p2_int_retzero : in std_logic;
-- Signals to/from the VME core. -- Signals to/from the VME core.
-- Directions inverted relative to the core. -- Directions inverted relative to the core.
...@@ -70,6 +74,7 @@ entity vme_cli_arb is ...@@ -70,6 +74,7 @@ entity vme_cli_arb is
signal vc_int_data_strobe : in std_logic := c_DATA_CLEAR; signal vc_int_data_strobe : in std_logic := c_DATA_CLEAR;
signal vc_int_go_consumed_strobe : in std_logic := '0'; signal vc_int_go_consumed_strobe : in std_logic := '0';
signal vc_int_blt_decision : in std_logic := '0'; signal vc_int_blt_decision : in std_logic := '0';
signal vc_int_blt_decided_consumed : in std_logic := '0';
signal vc_int_err_code : in err_vec_t := C_ERR_OK; signal vc_int_err_code : in err_vec_t := C_ERR_OK;
signal vc_int_addr : out vme_addr_t; signal vc_int_addr : out vme_addr_t;
...@@ -81,7 +86,8 @@ entity vme_cli_arb is ...@@ -81,7 +86,8 @@ entity vme_cli_arb is
signal vc_int_blt_decided : out std_logic; signal vc_int_blt_decided : out std_logic;
signal vc_int_blt_continue : out std_logic; signal vc_int_blt_continue : out std_logic;
signal vc_int_berr_ok : out std_logic signal vc_int_berr_ok : out std_logic;
signal vc_int_retzero : out std_logic
-- -- Dropped signals (since they cannot be multiplexed / -- -- Dropped signals (since they cannot be multiplexed /
-- -- span multiple access cycles). -- -- span multiple access cycles).
...@@ -201,6 +207,7 @@ begin ...@@ -201,6 +207,7 @@ begin
vc_int_blt_decided <= p1_int_blt_decided when live_1 else p2_int_blt_decided; vc_int_blt_decided <= p1_int_blt_decided when live_1 else p2_int_blt_decided;
vc_int_blt_continue <= p1_int_blt_continue when live_1 else p2_int_blt_continue; vc_int_blt_continue <= p1_int_blt_continue when live_1 else p2_int_blt_continue;
vc_int_berr_ok <= p1_int_berr_ok when live_1 else p2_int_berr_ok; vc_int_berr_ok <= p1_int_berr_ok when live_1 else p2_int_berr_ok;
vc_int_retzero <= p1_int_retzero when live_1 else p2_int_retzero;
-- Signals to the clients from the VME core: -- Signals to the clients from the VME core:
...@@ -230,6 +237,9 @@ begin ...@@ -230,6 +237,9 @@ begin
p1_int_blt_decision <= vc_int_blt_decision when live_1 else '0'; p1_int_blt_decision <= vc_int_blt_decision when live_1 else '0';
p2_int_blt_decision <= vc_int_blt_decision when live_2 else '0'; p2_int_blt_decision <= vc_int_blt_decision when live_2 else '0';
p1_int_blt_decided_consumed <= vc_int_blt_decided_consumed when live_1 else '0';
p2_int_blt_decided_consumed <= vc_int_blt_decided_consumed when live_2 else '0';
-- The busy of a client is simply while it is live. -- The busy of a client is simply while it is live.
-- This actually means that we will report busy some cycles -- This actually means that we will report busy some cycles
-- early. (But the clients are not likely to use this signal...) -- early. (But the clients are not likely to use this signal...)
......
...@@ -33,6 +33,7 @@ entity vme_core_arb is ...@@ -33,6 +33,7 @@ entity vme_core_arb is
signal cli_int_data_strobe : out std_logic := c_DATA_CLEAR; signal cli_int_data_strobe : out std_logic := c_DATA_CLEAR;
signal cli_int_go_consumed_strobe : out std_logic := '0'; signal cli_int_go_consumed_strobe : out std_logic := '0';
signal cli_int_blt_decision : out std_logic := '0'; signal cli_int_blt_decision : out std_logic := '0';
signal cli_int_blt_decided_consumed : out std_logic := '0';
signal cli_int_err_code : out err_vec_t := C_ERR_OK; signal cli_int_err_code : out err_vec_t := C_ERR_OK;
signal cli_int_addr : in vme_addr_t; signal cli_int_addr : in vme_addr_t;
...@@ -45,6 +46,7 @@ entity vme_core_arb is ...@@ -45,6 +46,7 @@ entity vme_core_arb is
signal cli_int_blt_continue : in std_logic; signal cli_int_blt_continue : in std_logic;
signal cli_int_berr_ok : in std_logic; signal cli_int_berr_ok : in std_logic;
signal cli_int_retzero : in std_logic;
-- Signals to/from the first VME core. -- Signals to/from the first VME core.
-- Directions inverted relative to the core. -- Directions inverted relative to the core.
...@@ -54,6 +56,7 @@ entity vme_core_arb is ...@@ -54,6 +56,7 @@ entity vme_core_arb is
signal vc1_int_data_strobe : in std_logic := c_DATA_CLEAR; signal vc1_int_data_strobe : in std_logic := c_DATA_CLEAR;
signal vc1_int_go_consumed_strobe : in std_logic := '0'; signal vc1_int_go_consumed_strobe : in std_logic := '0';
signal vc1_int_blt_decision : in std_logic := '0'; signal vc1_int_blt_decision : in std_logic := '0';
signal vc1_int_blt_decided_consumed : in std_logic := '0';
signal vc1_int_err_code : in err_vec_t := C_ERR_OK; signal vc1_int_err_code : in err_vec_t := C_ERR_OK;
signal vc1_int_addr : out vme_addr_t; signal vc1_int_addr : out vme_addr_t;
...@@ -66,6 +69,7 @@ entity vme_core_arb is ...@@ -66,6 +69,7 @@ entity vme_core_arb is
signal vc1_int_blt_continue : out std_logic; signal vc1_int_blt_continue : out std_logic;
signal vc1_int_berr_ok : out std_logic; signal vc1_int_berr_ok : out std_logic;
signal vc1_int_retzero : out std_logic;
-- Signals to/from the second VME core. -- Signals to/from the second VME core.
-- Directions inverted relative to the core. -- Directions inverted relative to the core.
...@@ -75,6 +79,7 @@ entity vme_core_arb is ...@@ -75,6 +79,7 @@ entity vme_core_arb is
signal vc2_int_data_strobe : in std_logic := c_DATA_CLEAR; signal vc2_int_data_strobe : in std_logic := c_DATA_CLEAR;
signal vc2_int_go_consumed_strobe : in std_logic := '0'; signal vc2_int_go_consumed_strobe : in std_logic := '0';
signal vc2_int_blt_decision : in std_logic := '0'; signal vc2_int_blt_decision : in std_logic := '0';
signal vc2_int_blt_decided_consumed : in std_logic := '0';
signal vc2_int_err_code : in err_vec_t := C_ERR_OK; signal vc2_int_err_code : in err_vec_t := C_ERR_OK;
signal vc2_int_addr : out vme_addr_t; signal vc2_int_addr : out vme_addr_t;
...@@ -86,56 +91,72 @@ entity vme_core_arb is ...@@ -86,56 +91,72 @@ entity vme_core_arb is
signal vc2_int_blt_decided : out std_logic; signal vc2_int_blt_decided : out std_logic;
signal vc2_int_blt_continue : out std_logic; signal vc2_int_blt_continue : out std_logic;
signal vc2_int_berr_ok : out std_logic signal vc2_int_berr_ok : out std_logic;
signal vc2_int_retzero : out std_logic
); );
end entity; end entity;
architecture rtl of vme_core_arb is architecture rtl of vme_core_arb is
signal core_1 : boolean := true; signal core_1_req : boolean := true;
signal addr_magic_slv : std_logic_vector(cli_int_addr'high downto cli_int_addr'high - 8 + 1); signal addr_magic_slv : std_logic_vector(cli_int_addr'high downto cli_int_addr'high - 8 + 1);
begin begin
-- cli_busy <= '1' when vc1_busy = '1' or vc2_busy = '1' else '0'; -- cli_busy <= '1' when vc1_busy = '1' or vc2_busy = '1' else '0';
cli_busy <= vc1_busy or vc2_busy;
cli_int_data_strobe <= vc1_int_data_strobe or vc2_int_data_strobe;
cli_int_blt_decision <= vc1_int_blt_decision or vc2_int_blt_decision;
cli_int_go_consumed_strobe <= vc1_int_go_consumed_strobe or vc2_int_go_consumed_strobe;
cli_int_data_read <= vc1_int_data_read when core_1 else vc2_int_data_read;
cli_int_err_code <= vc1_int_err_code when core_1 else vc2_int_err_code;
-- We or together all flags
cli_busy <= vc1_busy or vc2_busy;
cli_int_data_strobe <= vc1_int_data_strobe or vc2_int_data_strobe;
cli_int_blt_decision <= vc1_int_blt_decision or vc2_int_blt_decision;
cli_int_blt_decided_consumed <= vc1_int_blt_decided_consumed or vc2_int_blt_decided_consumed;
cli_int_go_consumed_strobe <= vc1_int_go_consumed_strobe or vc2_int_go_consumed_strobe;
-- We send all signals except go to both cores
vc1_int_addr <= cli_int_addr; vc1_int_addr <= cli_int_addr;
vc1_int_data_write <= cli_int_data_write; vc1_int_data_write <= cli_int_data_write;
vc1_int_am_i <= cli_int_am_i; vc1_int_am_i <= cli_int_am_i;
vc1_int_vme_write <= cli_int_vme_write; vc1_int_vme_write <= cli_int_vme_write;
vc1_int_blt_decided <= cli_int_blt_decided; vc1_int_blt_decided <= cli_int_blt_decided;
vc1_int_blt_continue <= cli_int_blt_continue; vc1_int_blt_continue <= cli_int_blt_continue;
vc1_int_berr_ok <= cli_int_berr_ok; vc1_int_berr_ok <= cli_int_berr_ok;
vc1_int_retzero <= cli_int_retzero;
vc2_int_addr <= cli_int_addr; vc2_int_addr <= cli_int_addr;
vc2_int_data_write <= cli_int_data_write; vc2_int_data_write <= cli_int_data_write;
vc2_int_am_i <= cli_int_am_i; vc2_int_am_i <= cli_int_am_i;
vc2_int_vme_write <= cli_int_vme_write; vc2_int_vme_write <= cli_int_vme_write;
vc2_int_blt_decided <= cli_int_blt_decided; vc2_int_blt_decided <= cli_int_blt_decided;
vc2_int_blt_continue <= cli_int_blt_continue; vc2_int_blt_continue <= cli_int_blt_continue;
vc2_int_berr_ok <= cli_int_berr_ok; vc2_int_berr_ok <= cli_int_berr_ok;
vc2_int_retzero <= cli_int_retzero;
-- Select core based on AM code
G_AM_SELECT : if am_select generate G_AM_SELECT : if am_select generate
core_1 <= cli_int_am_i /= am_magic; core_1_req <= cli_int_am_i /= am_magic and cli_int_retzero = '0';
end generate; end generate;
-- Select core based on ADDR lines
G_ADDR_SELECT : if addr_select generate G_ADDR_SELECT : if addr_select generate
addr_magic_slv <= std_logic_vector(to_unsigned(addr_magic, addr_magic_slv'length)); addr_magic_slv <= std_logic_vector(to_unsigned(addr_magic, addr_magic_slv'length));
core_1 <= addr_magic_slv /= core_1_req <= addr_magic_slv /=
cli_int_addr(addr_magic_slv'high downto addr_magic_slv'low); cli_int_addr(addr_magic_slv'high downto addr_magic_slv'low)
and cli_int_retzero = '0';
end generate; end generate;
-- Only issue a GO if the other core is _not_ busy
vc1_int_vme_go <= '1' when (cli_int_vme_go = '1'
and core_1_req and vc2_busy = '0')
else '0';
vc1_int_vme_go <= '1' when cli_int_vme_go = '1' and core_1 else '0'; vc2_int_vme_go <= '1' when (cli_int_vme_go = '1'
vc2_int_vme_go <= '1' when cli_int_vme_go = '1' and not core_1 else '0'; and not core_1_req and vc1_busy = '0')
else '0';
-- Forward data and err from the busy core
cli_int_data_read <= vc1_int_data_read when vc1_int_data_strobe = '1' else vc2_int_data_read;
cli_int_err_code <= vc1_int_err_code when vc1_int_data_strobe = '1' else vc2_int_err_code;
end architecture; end architecture;
......
...@@ -166,6 +166,10 @@ entity vme_data_bus is ...@@ -166,6 +166,10 @@ entity vme_data_bus is
-- See int_blt_decided and int_blt_continue -- See int_blt_decided and int_blt_continue
signal int_blt_decision : out std_logic := '0'; signal int_blt_decision : out std_logic := '0';
-- Strobe that indicates that the BLT decision has
-- been consumed.
signal int_blt_decided_consumed : out std_logic := '0';
-- Error code. -- Error code.
-- Consult vme_pkg.ERR_CODE for valid values. -- Consult vme_pkg.ERR_CODE for valid values.
-- Will be vme_pkg.ERR_CODE.OK if no problems. -- Will be vme_pkg.ERR_CODE.OK if no problems.
...@@ -294,6 +298,7 @@ begin ...@@ -294,6 +298,7 @@ begin
-- Strobes are by default '0', and only set when fired -- Strobes are by default '0', and only set when fired
int_data_strobe <= c_DATA_CLEAR; int_data_strobe <= c_DATA_CLEAR;
int_go_consumed_strobe <= '0'; int_go_consumed_strobe <= '0';
int_blt_decided_consumed <= '0';
-- Common delay counter -- Common delay counter
if (n_wait /= 0) then if (n_wait /= 0) then
...@@ -381,6 +386,10 @@ begin ...@@ -381,6 +386,10 @@ begin
data_placed <= '1'; data_placed <= '1';
end if; end if;
-- Prepare to drive strobes
vme_as_n_dir <= c_PIN_OUT;
vme_ds_n_dir <= c_PIN_OUT;
n_wait <= c_N_AS_DELAY; n_wait <= c_N_AS_DELAY;
state <= AS_DELAY; state <= AS_DELAY;
end if; end if;
...@@ -628,6 +637,7 @@ begin ...@@ -628,6 +637,7 @@ begin
when BLT_WRITE_WAIT => when BLT_WRITE_WAIT =>
if int_blt_decided = '1' then if int_blt_decided = '1' then
int_blt_decision <= '0'; int_blt_decision <= '0';
int_blt_decided_consumed <= '1';
if int_blt_continue = '1' then if int_blt_continue = '1' then
l_data_w <= int_data_write; -- Latch new data l_data_w <= int_data_write; -- Latch new data
...@@ -644,6 +654,7 @@ begin ...@@ -644,6 +654,7 @@ begin
when BLT_READ_WAIT => when BLT_READ_WAIT =>
if int_blt_decided = '1' then if int_blt_decided = '1' then
int_blt_decision <= '0'; int_blt_decision <= '0';
int_blt_decided_consumed <= '1';
if int_blt_continue = '1' then if int_blt_continue = '1' then
state <= DTACK_HIGH_WAIT; state <= DTACK_HIGH_WAIT;
else else
......
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