Commit aa578d26 authored by Michael Munch's avatar Michael Munch
Browse files

TB for client arb + bugfix

parent 701c2a1a
Pipeline #25497 failed with stage
in 10 seconds
......@@ -13,7 +13,7 @@ ui = VUnit.from_argv()
ui.add_osvvm()
ui.enable_location_preprocessing()
ui.add_array_util()
lib = ui.add_library("lib")
lib = ui.add_library("vme")
lib.add_source_files(join(root, "src", "*.vhd"))
lib.add_source_files(join(root, "src", "test", "*.vhd"))
lib.add_source_files(join(root, "src", "test", "tb_vme_cli_arb.vhd"))
ui.main()
......@@ -55,8 +55,6 @@ architecture tb of tb_vme_bus is
signal vme_ds_n_dir : std_logic;
signal vme_berr_n_i : std_logic;
signal vme_berr_n_o : std_logic;
signal vme_berr_n_dir : std_logic;
-- Request bus
signal vme_br_n_o : std_logic_vector(3 downto 0);
......@@ -105,8 +103,6 @@ begin
check_equal(vme_as_n_dir, c_PIN_IN);
-- iack default to input mode")
check_equal(vme_iack_n_dir, c_PIN_IN);
-- berr default to input mode")
check_equal(vme_berr_n_dir, c_PIN_IN);
-- data default to input mode")
check_equal(vme_data_dir, c_PIN_IN);
-- am default to input mode")
......@@ -899,8 +895,6 @@ begin
vme_ds_n_dir => vme_ds_n_dir,
vme_berr_n_i => vme_berr_n_i,
-- vme_berr_n_o => vme_berr_n_o,
vme_berr_n_dir => vme_berr_n_dir,
-- Request bus
vme_br_n_o => vme_br_n_o,
......@@ -924,6 +918,8 @@ begin
int_err_code => int_err_code,
int_data_strobe => int_data_strobe,
int_blt_decided => int_blt_decided,
int_blt_continue => int_blt_continue
int_blt_continue => int_blt_continue,
int_timeout_n => '0'
);
end architecture;
library vunit_lib;
context vunit_lib.vunit_context;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme_pkg.all;
entity tb_vme_bus is
generic (runner_cfg : string);
end entity;
architecture tb of tb_vme_bus is
signal clk : std_logic := '0';
-- Signals to/from the first client.
-- For documentation on the signal purposes, see vme_bus.vhd.
signal p1_busy : std_logic := '0';
signal p1_int_data_o : vme_vec_64_t;
signal p1_int_data_strobe : std_logic := c_DATA_CLEAR;
signal p1_int_go_consumed_strobe : std_logic := '0';
signal p1_int_blt_decision_strobe : std_logic := '0';
signal p1_int_err_code : err_vec_t := C_ERR_OK;
signal p1_int_addr : vme_addr_t;
signal p1_int_data_i : vme_vec_64_t;
signal p1_int_am_i : am_vec_t;
signal p1_int_vme_rw : std_logic := '0';
signal p1_int_vme_go : std_logic := '0';
signal p1_int_blt_decided : std_logic;
signal p1_int_blt_continue : std_logic;
signal p1_int_berr_ok : std_logic;
-- Signals to/from the second client.
signal p2_busy : std_logic := '0';
signal p2_int_data_o : vme_vec_64_t;
signal p2_int_data_strobe : std_logic := c_DATA_CLEAR;
signal p2_int_go_consumed_strobe : std_logic := '0';
signal p2_int_blt_decision_strobe : std_logic := '0';
signal p2_int_err_code : err_vec_t := C_ERR_OK;
signal p2_int_addr : vme_addr_t;
signal p2_int_data_i : vme_vec_64_t;
signal p2_int_am_i : am_vec_t;
signal p2_int_vme_rw : std_logic := '0';
signal p2_int_vme_go : std_logic := '0';
signal p2_int_blt_decided : std_logic;
signal p2_int_blt_continue : std_logic;
signal p2_int_berr_ok : std_logic;
-- Signals to/from the VME core.
-- Directions inverted relative to the core.
-- Core 1
signal vc1_busy : std_logic := '0';
signal vc1_int_data_o : vme_vec_64_t;
signal vc1_int_data_strobe : std_logic := c_DATA_CLEAR;
signal vc1_int_go_consumed_strobe : std_logic := '0';
signal vc1_int_blt_decision_strobe : std_logic := '0';
signal vc1_int_err_code : err_vec_t := C_ERR_OK;
signal vc1_int_addr : vme_addr_t;
signal vc1_int_data_i : vme_vec_64_t;
signal vc1_int_am_i : am_vec_t;
signal vc1_int_vme_rw : std_logic;
signal vc1_int_vme_go : std_logic;
signal vc1_int_blt_decided : std_logic;
signal vc1_int_blt_continue : std_logic;
signal vc1_int_berr_ok : std_logic;
-- Core 2
signal vc2_busy : std_logic := '0';
signal vc2_int_data_o : vme_vec_64_t;
signal vc2_int_data_strobe : std_logic := c_DATA_CLEAR;
signal vc2_int_go_consumed_strobe : std_logic := '0';
signal vc2_int_blt_decision_strobe : std_logic := '0';
signal vc2_int_err_code : err_vec_t := C_ERR_OK;
signal vc2_int_addr : vme_addr_t;
signal vc2_int_data_i : vme_vec_64_t;
signal vc2_int_am_i : am_vec_t;
signal vc2_int_vme_rw : std_logic;
signal vc2_int_vme_go : std_logic;
signal vc2_int_blt_decided : std_logic;
signal vc2_int_blt_continue : std_logic;
signal vc2_int_berr_ok : std_logic;
begin
main: process
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("p1 read with AM=0x39 is directed to core 1") then
wait for 10 ns;
p1_int_am_i <= "111001"; -- 0x39
p1_int_addr <= X"12345678";
p1_int_vme_go <= '1';
p2_int_vme_go <= '0';
wait for 10 ns;
check_equal(vc1_int_vme_go, '1');
p1_int_vme_go <= '0';
wait for 10 ns;
check_equal(p1_int_vme_go, '0');
elsif run("p1 read with AM=0x19 is directed to core 2") then
wait for 10 ns;
p1_int_am_i <= "011001"; -- 0x19
p1_int_addr <= X"12345678";
p1_int_vme_go <= '1';
p2_int_vme_go <= '0';
wait for 10 ns;
check_equal(vc1_int_vme_go, '0');
check_equal(vc2_int_vme_go, '1');
p1_int_vme_go <= '0';
wait for 10 ns;
check_equal(p1_int_vme_go, '0');
end if;
end loop;
test_runner_cleanup(runner); -- Simulation ends here
end process;
clk <= not clk after 5 ns;
test_runner_watchdog(runner, 250 ns);
dut : entity work.vme_cli_arb
port map (clk => clk,
p1_busy => p1_busy,
p1_int_data_o => p1_int_data_o,
p1_int_data_strobe => p1_int_data_strobe,
p1_int_go_consumed_strobe => p1_int_go_consumed_strobe,
p1_int_blt_decision_strobe => p1_int_blt_decision_strobe,
p1_int_err_code => p1_int_err_code,
p1_int_addr => p1_int_addr,
p1_int_data_i => p1_int_data_i,
p1_int_am_i => p1_int_am_i,
p1_int_vme_rw => p1_int_vme_rw,
p1_int_vme_go => p1_int_vme_go,
p1_int_blt_decided => p1_int_blt_decided,
p1_int_blt_continue => p1_int_blt_continue,
p1_int_berr_ok => p1_int_berr_ok,
-- Signals to/from the second client.
p2_busy => p2_busy,
p2_int_data_o => p2_int_data_o,
p2_int_data_strobe => p2_int_data_strobe,
p2_int_go_consumed_strobe => p2_int_go_consumed_strobe,
p2_int_blt_decision_strobe => p2_int_blt_decision_strobe,
p2_int_err_code => p2_int_err_code,
p2_int_addr => p2_int_addr,
p2_int_data_i => p2_int_data_i,
p2_int_am_i => p2_int_am_i,
p2_int_vme_rw => p2_int_vme_rw,
p2_int_vme_go => p2_int_vme_go,
p2_int_blt_decided => p2_int_blt_decided,
p2_int_blt_continue => p2_int_blt_continue,
p2_int_berr_ok => p2_int_berr_ok,
-- Core 1
vc1_busy => vc1_busy,
vc1_int_data_o => vc1_int_data_o,
vc1_int_data_strobe => vc1_int_data_strobe,
vc1_int_go_consumed_strobe => vc1_int_go_consumed_strobe,
vc1_int_blt_decision_strobe => vc1_int_blt_decision_strobe,
vc1_int_err_code => vc1_int_err_code,
vc1_int_addr => vc1_int_addr,
vc1_int_data_i => vc1_int_data_i,
vc1_int_am_i => vc1_int_am_i,
vc1_int_vme_rw => vc1_int_vme_rw,
vc1_int_vme_go => vc1_int_vme_go,
vc1_int_blt_decided => vc1_int_blt_decided,
vc1_int_blt_continue => vc1_int_blt_continue,
vc1_int_berr_ok => vc1_int_berr_ok,
-- Core 2
vc2_busy => vc2_busy,
vc2_int_data_o => vc2_int_data_o,
vc2_int_data_strobe => vc2_int_data_strobe,
vc2_int_go_consumed_strobe => vc2_int_go_consumed_strobe,
vc2_int_blt_decision_strobe => vc2_int_blt_decision_strobe,
vc2_int_err_code => vc2_int_err_code,
vc2_int_addr => vc2_int_addr,
vc2_int_data_i => vc2_int_data_i,
vc2_int_am_i => vc2_int_am_i,
vc2_int_vme_rw => vc2_int_vme_rw,
vc2_int_vme_go => vc2_int_vme_go,
vc2_int_blt_decided => vc2_int_blt_decided,
vc2_int_blt_continue => vc2_int_blt_continue,
vc2_int_berr_ok => vc2_int_berr_ok
);
end architecture;
......@@ -194,6 +194,10 @@ begin
live_1 <= (active_1 and r_busy = '1') or start_1;
live_2 <= (active_2 and r_busy = '1') or start_2;
-- Only AM=0x19 are passed to core 2.
core_1 <= p1_int_am_i /= c_AM_TRLOII when live_1 else
p2_int_am_i /= c_AM_TRLOII;
process (clk)
begin
if (rising_edge(clk)) then
......@@ -212,19 +216,11 @@ begin
-- client directly.
if (start_1) then
active_1 <= true;
prefer_1 <= false;
-- Only AM=0x19 are passed to core 2.
-- core_1 <= p1_int_am_i /= X"19";
core_1 <= false;
prefer_1 <= false;
end if;
if (start_2) then
active_2 <= true;
prefer_1 <= true;
-- Only AM=0x19 are passed to core 2.
-- core_1 <= p2_int_am_i /= X"19";
core_1 <= false;
end if;
-- We select on active instead of live, since active is cheaper (comes
......
......@@ -61,6 +61,9 @@ package vme_pkg is
constant c_AM_A60 : am_vec_t := "000001"; -- 0x01
constant c_AM_A60_MBLT : am_vec_t := "000000"; -- 0x00
-- User defined AM code used for TRLOII communication
constant c_AM_TRLOII : am_vec_t := "011001"; -- 0x19
constant c_PIN_OUT : std_logic := '1';
constant c_PIN_IN : std_logic := '0';
......
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