Revert "Clocked core arbiter"

This reverts commit fd7a53fe.

src/vme_core_arb.vhd

@@ -87,48 +87,38 @@ end entity;
 
 
 architecture rtl of vme_core_arb is
+  signal core_1                  : boolean := true;
 begin
-  process(clk)
-  begin
-    if (rising_edge(clk)) then
-      if (cli_int_am_i = c_AM_TRLOII) then
-        cli_busy                     <= vc1_busy;
-        cli_int_data_strobe          <= vc1_int_go_consumed_strobe;
-        cli_int_blt_decision_strobe  <= vc1_int_blt_decision_strobe; 
-        cli_int_go_consumed_strobe   <= vc1_int_go_consumed_strobe;
-        cli_int_data_o               <= vc1_int_data_o; 
-        cli_int_err_code             <= vc1_int_err_code;
-
-        vc1_int_vme_go <= cli_int_vme_go;
-        vc2_int_vme_go <= '0';
-      else
-        cli_busy                     <= vc2_busy;
-        cli_int_data_strobe          <= vc2_int_go_consumed_strobe;
-        cli_int_blt_decision_strobe  <= vc2_int_blt_decision_strobe; 
-        cli_int_go_consumed_strobe   <= vc2_int_go_consumed_strobe;
-        cli_int_data_o               <= vc2_int_data_o; 
-        cli_int_err_code             <= vc2_int_err_code;
-
-        vc1_int_vme_go <= '0';
-        vc2_int_vme_go <= cli_int_vme_go;
-      end if;
-      vc1_int_addr                   <= cli_int_addr;
-      vc1_int_data_i                 <= cli_int_data_i;
-      vc1_int_am_i                   <= cli_int_am_i;
-      vc1_int_vme_rw                 <= cli_int_vme_rw;
-      vc1_int_blt_decided            <= cli_int_blt_decided;
-      vc1_int_blt_continue           <= cli_int_blt_continue;
-      vc1_int_berr_ok                <= cli_int_berr_ok;
-
-      vc2_int_addr                   <= cli_int_addr;
-      vc2_int_data_i                 <= cli_int_data_i;
-      vc2_int_am_i                   <= cli_int_am_i;
-      vc2_int_vme_rw                 <= cli_int_vme_rw;
-      vc2_int_blt_decided            <= cli_int_blt_decided;
-      vc2_int_blt_continue           <= cli_int_blt_continue;
-      vc2_int_berr_ok                <= cli_int_berr_ok;      
-    end if;
-  end process;
+
+  -- cli_busy <= '1' when vc1_busy = '1' or vc2_busy = '1' else '0';
+  cli_busy                     <= vc1_busy                    or vc2_busy                   ;
+  cli_int_data_strobe          <= vc1_int_go_consumed_strobe  or vc2_int_go_consumed_strobe ;
+  cli_int_blt_decision_strobe  <= vc1_int_blt_decision_strobe or vc2_int_blt_decision_strobe;
+  cli_int_go_consumed_strobe   <= vc1_int_go_consumed_strobe  or vc2_int_go_consumed_strobe ;
+  
+  cli_int_data_o               <= vc1_int_data_o              when core_1 else vc2_int_data_o;
+  cli_int_err_code             <= vc1_int_err_code            when core_1 else vc2_int_err_code;
+
+  vc1_int_addr           <= cli_int_addr;
+  vc1_int_data_i         <= cli_int_data_i;
+  vc1_int_am_i           <= cli_int_am_i;
+  vc1_int_vme_rw         <= cli_int_vme_rw;
+  vc1_int_blt_decided    <= cli_int_blt_decided;
+  vc1_int_blt_continue   <= cli_int_blt_continue;
+  vc1_int_berr_ok        <= cli_int_berr_ok;
+
+  vc2_int_addr           <= cli_int_addr;
+  vc2_int_data_i         <= cli_int_data_i;
+  vc2_int_am_i           <= cli_int_am_i;
+  vc2_int_vme_rw         <= cli_int_vme_rw;
+  vc2_int_blt_decided    <= cli_int_blt_decided;
+  vc2_int_blt_continue   <= cli_int_blt_continue;
+  vc2_int_berr_ok        <= cli_int_berr_ok;
+
+
+  core_1 <= cli_int_am_i /= c_AM_TRLOII;
+  vc1_int_vme_go <= '1' when cli_int_vme_go = '1' and core_1 else '0';
+  vc2_int_vme_go <= '1' when cli_int_vme_go = '1' and not core_1 else '0';
 end architecture;