vme_data_bus will also issue data_strobe on writes

src/vme_data_bus.vhd

@@ -513,15 +513,18 @@ begin
                   vme_as_n_o <= '1';
                   state <= IDLE;
                   busy <= '0';
+                  int_data_strobe <= c_DATA_PRESENT;
                   int_err_code <= c_ERR_OK;
                 when BLT =>
                   -- Per Rule 2.34a there must be 40ns delay
                   -- between DS* transistions. Handle this in next cycle
                   int_blt_decision_strobe <= '1';
+                  int_data_strobe <= c_DATA_PRESENT;
                   state <= BLT_WRITE_WAIT;
                 when MBLT =>
                   if first_cycle = '0' then
                     int_blt_decision_strobe <= '1';
+                    int_data_strobe <= c_DATA_PRESENT;
                     state <= BLT_WRITE_WAIT;
                   else
                     -- ADDR broadcast. Now write data.
@@ -607,6 +610,7 @@ begin
           l_data <= cur_data;
 
         when BLT_WRITE_WAIT =>
+          int_data_strobe <= c_DATA_CLEAR;
           if int_blt_decided = '1' then
             int_blt_decision_strobe <= '0';