Commit 959d3636 authored by Michael Munch's avatar Michael Munch
Browse files

int_data_i -> int_data_write && int_data_o -> int_data_read

parent 2bde4812
Pipeline #25925 failed with stage
in 36 seconds
...@@ -72,8 +72,8 @@ architecture tb of tb_vme_bus is ...@@ -72,8 +72,8 @@ architecture tb of tb_vme_bus is
signal busy : std_logic; signal busy : std_logic;
signal int_addr : std_logic_vector(31 downto 0); signal int_addr : std_logic_vector(31 downto 0);
signal int_data_i : std_logic_vector(63 downto 0); signal int_data_write : std_logic_vector(63 downto 0);
signal int_data_o : std_logic_vector(63 downto 0); signal int_data_read : std_logic_vector(63 downto 0);
signal int_am_i : am_vec_t; signal int_am_i : am_vec_t;
signal int_vme_write : std_logic; signal int_vme_write : std_logic;
...@@ -209,7 +209,7 @@ begin ...@@ -209,7 +209,7 @@ begin
int_vme_write <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_write <= (others => '1');
wait for 20 ns; wait for 20 ns;
check_equal(vme_addr_dir, c_PIN_OUT); check_equal(vme_addr_dir, c_PIN_OUT);
...@@ -217,7 +217,7 @@ begin ...@@ -217,7 +217,7 @@ begin
check_equal(vme_iack_n_dir, c_PIN_OUT); check_equal(vme_iack_n_dir, c_PIN_OUT);
check_equal(vme_addr_o, int_addr); check_equal(vme_addr_o, int_addr);
check_equal(vme_data_dir, c_PIN_OUT); check_equal(vme_data_dir, c_PIN_OUT);
check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0)); check_equal(vme_data_o(31 downto 0), int_data_write(31 downto 0));
elsif run("if SiCy WRITE and slave ack then FSM => IDLE") then elsif run("if SiCy WRITE and slave ack then FSM => IDLE") then
...@@ -226,7 +226,7 @@ begin ...@@ -226,7 +226,7 @@ begin
int_vme_write <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_write <= (others => '1');
wait for 20 ns; wait for 20 ns;
int_vme_go <= '0'; int_vme_go <= '0';
...@@ -236,7 +236,7 @@ begin ...@@ -236,7 +236,7 @@ begin
check_equal(vme_iack_n_dir, c_PIN_OUT); check_equal(vme_iack_n_dir, c_PIN_OUT);
check_equal(vme_addr_o, int_addr); check_equal(vme_addr_o, int_addr);
check_equal(vme_data_dir, c_PIN_OUT); check_equal(vme_data_dir, c_PIN_OUT);
check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0)); check_equal(vme_data_o(31 downto 0), int_data_write(31 downto 0));
wait for 40 ns; wait for 40 ns;
check_equal(vme_ds_n_o, unsigned'(B"00")); check_equal(vme_ds_n_o, unsigned'(B"00"));
...@@ -261,7 +261,7 @@ begin ...@@ -261,7 +261,7 @@ begin
int_vme_write <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_write <= (others => '1');
wait for 20 ns; wait for 20 ns;
check_equal(vme_addr_dir, c_PIN_OUT); check_equal(vme_addr_dir, c_PIN_OUT);
...@@ -269,7 +269,7 @@ begin ...@@ -269,7 +269,7 @@ begin
check_equal(vme_iack_n_dir, c_PIN_OUT); check_equal(vme_iack_n_dir, c_PIN_OUT);
check_equal(vme_addr_o, int_addr); check_equal(vme_addr_o, int_addr);
check_equal(vme_data_dir, c_PIN_OUT); check_equal(vme_data_dir, c_PIN_OUT);
check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0)); check_equal(vme_data_o(31 downto 0), int_data_write(31 downto 0));
check_equal(vme_as_n_dir, c_PIN_IN); check_equal(vme_as_n_dir, c_PIN_IN);
wait for 40 ns; wait for 40 ns;
...@@ -283,7 +283,7 @@ begin ...@@ -283,7 +283,7 @@ begin
int_vme_write <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_write <= (others => '1');
wait for 20 ns; wait for 20 ns;
check_equal(vme_addr_dir, c_PIN_OUT); check_equal(vme_addr_dir, c_PIN_OUT);
...@@ -302,7 +302,7 @@ begin ...@@ -302,7 +302,7 @@ begin
wait for 15 ns; wait for 15 ns;
check_equal(vme_data_dir, c_PIN_OUT); check_equal(vme_data_dir, c_PIN_OUT);
check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0)); check_equal(vme_data_o(31 downto 0), int_data_write(31 downto 0));
check_equal(vme_ds_n_dir, c_PIN_IN); check_equal(vme_ds_n_dir, c_PIN_IN);
...@@ -410,7 +410,7 @@ begin ...@@ -410,7 +410,7 @@ begin
check_equal(int_data_strobe, c_DATA_CLEAR); check_equal(int_data_strobe, c_DATA_CLEAR);
wait for 40 ns; wait for 40 ns;
check_equal(int_data_strobe, c_DATA_PRESENT); check_equal(int_data_strobe, c_DATA_PRESENT);
check_equal(int_data_o(31 downto 0), vme_data_i(31 downto 0)); check_equal(int_data_read(31 downto 0), vme_data_i(31 downto 0));
elsif run("During regular reads, when clients signal data read, FSM => IDLE") then elsif run("During regular reads, when clients signal data read, FSM => IDLE") then
...@@ -510,7 +510,7 @@ begin ...@@ -510,7 +510,7 @@ begin
wait for 40 ns; wait for 40 ns;
check_equal(int_data_strobe, c_DATA_PRESENT); check_equal(int_data_strobe, c_DATA_PRESENT);
check_equal(int_data_o(31 downto 0), vme_data_i(31 downto 0)); check_equal(int_data_read(31 downto 0), vme_data_i(31 downto 0));
check_equal(vme_ds_n_dir, c_PIN_OUT); check_equal(vme_ds_n_dir, c_PIN_OUT);
check_equal(vme_ds_n_o, unsigned'(B"11")); check_equal(vme_ds_n_o, unsigned'(B"11"));
...@@ -541,7 +541,7 @@ begin ...@@ -541,7 +541,7 @@ begin
wait for 40 ns; wait for 40 ns;
check_equal(int_data_strobe, c_DATA_PRESENT); check_equal(int_data_strobe, c_DATA_PRESENT);
check_equal(int_data_o(31 downto 0), vme_data_i(31 downto 0)); check_equal(int_data_read(31 downto 0), vme_data_i(31 downto 0));
check_equal(vme_ds_n_dir, c_PIN_OUT); check_equal(vme_ds_n_dir, c_PIN_OUT);
check_equal(vme_ds_n_o, unsigned'(B"11")); check_equal(vme_ds_n_o, unsigned'(B"11"));
...@@ -560,7 +560,7 @@ begin ...@@ -560,7 +560,7 @@ begin
vme_data_i <= (others => '0'); vme_data_i <= (others => '0');
wait for 40 ns; wait for 40 ns;
check_equal(int_data_strobe, c_DATA_PRESENT); check_equal(int_data_strobe, c_DATA_PRESENT);
check_equal(int_data_o(31 downto 0), vme_data_i(31 downto 0)); check_equal(int_data_read(31 downto 0), vme_data_i(31 downto 0));
elsif run("ADDR lines are released when DTACK* received in MBLT mode") then elsif run("ADDR lines are released when DTACK* received in MBLT mode") then
...@@ -665,7 +665,7 @@ begin ...@@ -665,7 +665,7 @@ begin
int_vme_write <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_MBLT; int_am_i <= c_AM_A24_MBLT;
int_addr <= (others => '0'); int_addr <= (others => '0');
int_data_i <= (others => '1'); int_data_write <= (others => '1');
wait for 20 ns; wait for 20 ns;
check_equal(int_err_code, c_ERR_OK); check_equal(int_err_code, c_ERR_OK);
...@@ -700,7 +700,7 @@ begin ...@@ -700,7 +700,7 @@ begin
int_vme_write <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_BLT; int_am_i <= c_AM_A24_BLT;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_write <= (others => '1');
wait for 20 ns; wait for 20 ns;
check_equal(int_err_code, c_ERR_OK); check_equal(int_err_code, c_ERR_OK);
...@@ -709,7 +709,7 @@ begin ...@@ -709,7 +709,7 @@ begin
check_equal(vme_iack_n_dir, c_PIN_OUT); check_equal(vme_iack_n_dir, c_PIN_OUT);
check_equal(vme_addr_o, int_addr); check_equal(vme_addr_o, int_addr);
check_equal(vme_data_dir, c_PIN_OUT); check_equal(vme_data_dir, c_PIN_OUT);
check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0)); check_equal(vme_data_o(31 downto 0), int_data_write(31 downto 0));
elsif run("if doing BLT write DS* goes high on slave ACK") then elsif run("if doing BLT write DS* goes high on slave ACK") then
...@@ -718,7 +718,7 @@ begin ...@@ -718,7 +718,7 @@ begin
int_vme_write <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_BLT; int_am_i <= c_AM_A24_BLT;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_write <= (others => '1');
wait for 20 ns; wait for 20 ns;
check_equal(int_err_code, c_ERR_OK); check_equal(int_err_code, c_ERR_OK);
...@@ -727,7 +727,7 @@ begin ...@@ -727,7 +727,7 @@ begin
check_equal(vme_iack_n_dir, c_PIN_OUT); check_equal(vme_iack_n_dir, c_PIN_OUT);
check_equal(vme_addr_o, int_addr); check_equal(vme_addr_o, int_addr);
check_equal(vme_data_dir, c_PIN_OUT); check_equal(vme_data_dir, c_PIN_OUT);
check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0)); check_equal(vme_data_o(31 downto 0), int_data_write(31 downto 0));
int_vme_go <= '0'; int_vme_go <= '0';
wait for 40 ns; wait for 40 ns;
...@@ -745,7 +745,7 @@ begin ...@@ -745,7 +745,7 @@ begin
int_vme_write <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_BLT; int_am_i <= c_AM_A24_BLT;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_write <= (others => '1');
wait for 20 ns; wait for 20 ns;
check_equal(int_err_code, c_ERR_OK); check_equal(int_err_code, c_ERR_OK);
...@@ -754,7 +754,7 @@ begin ...@@ -754,7 +754,7 @@ begin
check_equal(vme_iack_n_dir, c_PIN_OUT); check_equal(vme_iack_n_dir, c_PIN_OUT);
check_equal(vme_addr_o, int_addr); check_equal(vme_addr_o, int_addr);
check_equal(vme_data_dir, c_PIN_OUT); check_equal(vme_data_dir, c_PIN_OUT);
check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0)); check_equal(vme_data_o(31 downto 0), int_data_write(31 downto 0));
int_vme_go <= '0'; int_vme_go <= '0';
...@@ -780,7 +780,7 @@ begin ...@@ -780,7 +780,7 @@ begin
int_vme_write <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_BLT; int_am_i <= c_AM_A24_BLT;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_write <= (others => '1');
wait for 20 ns; wait for 20 ns;
check_equal(int_err_code, c_ERR_OK); check_equal(int_err_code, c_ERR_OK);
...@@ -789,7 +789,7 @@ begin ...@@ -789,7 +789,7 @@ begin
check_equal(vme_iack_n_dir, c_PIN_OUT); check_equal(vme_iack_n_dir, c_PIN_OUT);
check_equal(vme_addr_o, int_addr); check_equal(vme_addr_o, int_addr);
check_equal(vme_data_dir, c_PIN_OUT); check_equal(vme_data_dir, c_PIN_OUT);
check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0)); check_equal(vme_data_o(31 downto 0), int_data_write(31 downto 0));
int_vme_go <= '0'; int_vme_go <= '0';
int_blt_decided <= '0'; int_blt_decided <= '0';
...@@ -805,13 +805,13 @@ begin ...@@ -805,13 +805,13 @@ begin
-- Slave rescind -- Slave rescind
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
int_blt_decided <= '1'; int_blt_continue <= '1'; int_blt_decided <= '1'; int_blt_continue <= '1';
int_data_i <= (others => '0'); int_data_write <= (others => '0');
int_addr <= (others => '0'); int_addr <= (others => '0');
wait for 10 ns; -- BLT decision wait for 10 ns; -- BLT decision
wait for 10 ns; -- DTACK* detection wait for 10 ns; -- DTACK* detection
wait for 40 ns; -- D -> DS* delay wait for 40 ns; -- D -> DS* delay
check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0)); check_equal(vme_data_o(31 downto 0), int_data_write(31 downto 0));
check_equal(vme_ds_n_o, unsigned'(B"00")); check_equal(vme_ds_n_o, unsigned'(B"00"));
...@@ -955,8 +955,8 @@ begin ...@@ -955,8 +955,8 @@ begin
busy => busy, busy => busy,
int_addr => int_addr, int_addr => int_addr,
int_data_i => int_data_i, int_data_write => int_data_write,
int_data_o => int_data_o, int_data_read => int_data_read,
int_am_i => int_am_i, int_am_i => int_am_i,
int_vme_write => int_vme_write, int_vme_write => int_vme_write,
int_vme_go => int_vme_go, int_vme_go => int_vme_go,
......
...@@ -23,14 +23,14 @@ entity vme_cli_arb is ...@@ -23,14 +23,14 @@ entity vme_cli_arb is
signal p1_busy : out std_logic := '0'; signal p1_busy : out std_logic := '0';
signal p1_int_data_o : out vme_vec_64_t; signal p1_int_data_read : out vme_vec_64_t;
signal p1_int_data_strobe : out std_logic := c_DATA_CLEAR; signal p1_int_data_strobe : out std_logic := c_DATA_CLEAR;
signal p1_int_go_consumed_strobe : out std_logic := '0'; signal p1_int_go_consumed_strobe : out std_logic := '0';
signal p1_int_blt_decision : out std_logic := '0'; signal p1_int_blt_decision : out std_logic := '0';
signal p1_int_err_code : out err_vec_t := C_ERR_OK; signal p1_int_err_code : out err_vec_t := C_ERR_OK;
signal p1_int_addr : in vme_addr_t; signal p1_int_addr : in vme_addr_t;
signal p1_int_data_i : in vme_vec_64_t; signal p1_int_data_write : in vme_vec_64_t;
signal p1_int_am_i : in am_vec_t; signal p1_int_am_i : in am_vec_t;
signal p1_int_vme_write : in std_logic; signal p1_int_vme_write : in std_logic;
signal p1_int_vme_go : in std_logic; signal p1_int_vme_go : in std_logic;
...@@ -44,14 +44,14 @@ entity vme_cli_arb is ...@@ -44,14 +44,14 @@ entity vme_cli_arb is
signal p2_busy : out std_logic := '0'; signal p2_busy : out std_logic := '0';
signal p2_int_data_o : out vme_vec_64_t; signal p2_int_data_read : out vme_vec_64_t;
signal p2_int_data_strobe : out std_logic := c_DATA_CLEAR; signal p2_int_data_strobe : out std_logic := c_DATA_CLEAR;
signal p2_int_go_consumed_strobe : out std_logic := '0'; signal p2_int_go_consumed_strobe : out std_logic := '0';
signal p2_int_blt_decision : out std_logic := '0'; signal p2_int_blt_decision : out std_logic := '0';
signal p2_int_err_code : out err_vec_t := C_ERR_OK; signal p2_int_err_code : out err_vec_t := C_ERR_OK;
signal p2_int_addr : in vme_addr_t; signal p2_int_addr : in vme_addr_t;
signal p2_int_data_i : in vme_vec_64_t; signal p2_int_data_write : in vme_vec_64_t;
signal p2_int_am_i : in am_vec_t; signal p2_int_am_i : in am_vec_t;
signal p2_int_vme_write : in std_logic; signal p2_int_vme_write : in std_logic;
signal p2_int_vme_go : in std_logic; signal p2_int_vme_go : in std_logic;
...@@ -66,14 +66,14 @@ entity vme_cli_arb is ...@@ -66,14 +66,14 @@ entity vme_cli_arb is
signal vc_busy : in std_logic := '0'; signal vc_busy : in std_logic := '0';
signal vc_int_data_o : in vme_vec_64_t; signal vc_int_data_read : in vme_vec_64_t;
signal vc_int_data_strobe : in std_logic := c_DATA_CLEAR; signal vc_int_data_strobe : in std_logic := c_DATA_CLEAR;
signal vc_int_go_consumed_strobe : in std_logic := '0'; signal vc_int_go_consumed_strobe : in std_logic := '0';
signal vc_int_blt_decision : in std_logic := '0'; signal vc_int_blt_decision : in std_logic := '0';
signal vc_int_err_code : in err_vec_t := C_ERR_OK; signal vc_int_err_code : in err_vec_t := C_ERR_OK;
signal vc_int_addr : out vme_addr_t; signal vc_int_addr : out vme_addr_t;
signal vc_int_data_i : out vme_vec_64_t; signal vc_int_data_write : out vme_vec_64_t;
signal vc_int_am_i : out am_vec_t; signal vc_int_am_i : out am_vec_t;
signal vc_int_vme_write : out std_logic; signal vc_int_vme_write : out std_logic;
signal vc_int_vme_go : out std_logic; signal vc_int_vme_go : out std_logic;
...@@ -132,8 +132,8 @@ architecture rtl of vme_cli_arb is ...@@ -132,8 +132,8 @@ architecture rtl of vme_cli_arb is
-- no longer busy? -- no longer busy?
signal prefer_1 : boolean := false; signal prefer_1 : boolean := false;
signal p1_int_data_o_latched : vme_vec_64_t := (others => '0'); signal p1_int_data_read_latched : vme_vec_64_t := (others => '0');
signal p2_int_data_o_latched : vme_vec_64_t := (others => '0'); signal p2_int_data_read_latched : vme_vec_64_t := (others => '0');
signal p1_int_err_code_latched : err_vec_t := C_ERR_OK; signal p1_int_err_code_latched : err_vec_t := C_ERR_OK;
signal p2_int_err_code_latched : err_vec_t := C_ERR_OK; signal p2_int_err_code_latched : err_vec_t := C_ERR_OK;
...@@ -182,10 +182,10 @@ begin ...@@ -182,10 +182,10 @@ begin
-- directly from a flip-flop, instead of logic), and -- directly from a flip-flop, instead of logic), and
-- vc_int_data_strobe will not come on the first cycle. -- vc_int_data_strobe will not come on the first cycle.
if (active_1 and vc_int_data_strobe = '1') then if (active_1 and vc_int_data_strobe = '1') then
p1_int_data_o_latched <= vc_int_data_o; p1_int_data_read_latched <= vc_int_data_read;
end if; end if;
if (active_2 and vc_int_data_strobe = '1') then if (active_2 and vc_int_data_strobe = '1') then
p2_int_data_o_latched <= vc_int_data_o; p2_int_data_read_latched <= vc_int_data_read;
end if; end if;
end if; end if;
...@@ -199,7 +199,7 @@ begin ...@@ -199,7 +199,7 @@ begin
-- only react to anything if the 'go' signal is given. -- only react to anything if the 'go' signal is given.
vc_int_addr <= p1_int_addr when live_1 else p2_int_addr; vc_int_addr <= p1_int_addr when live_1 else p2_int_addr;
vc_int_data_i <= p1_int_data_i when live_1 else p2_int_data_i; vc_int_data_write <= p1_int_data_write when live_1 else p2_int_data_write;
vc_int_am_i <= p1_int_am_i when live_1 else p2_int_am_i; vc_int_am_i <= p1_int_am_i when live_1 else p2_int_am_i;
vc_int_vme_write <= p1_int_vme_write when live_1 else p2_int_vme_write; vc_int_vme_write <= p1_int_vme_write when live_1 else p2_int_vme_write;
vc_int_vme_go <= p1_int_vme_go when live_1 else p2_int_vme_go; vc_int_vme_go <= p1_int_vme_go when live_1 else p2_int_vme_go;
...@@ -215,10 +215,10 @@ begin ...@@ -215,10 +215,10 @@ begin
-- Data is passed directly through on the cycle they have been latched. -- Data is passed directly through on the cycle they have been latched.
-- Otherwise, take the latched value: -- Otherwise, take the latched value:
p1_int_data_o <= vc_int_data_o when (live_1 and vc_int_data_strobe = '1') else p1_int_data_read <= vc_int_data_read when (live_1 and vc_int_data_strobe = '1') else
p1_int_data_o_latched; p1_int_data_read_latched;
p2_int_data_o <= vc_int_data_o when (live_2 and vc_int_data_strobe = '1') else p2_int_data_read <= vc_int_data_read when (live_2 and vc_int_data_strobe = '1') else
p2_int_data_o_latched; p2_int_data_read_latched;
-- The error code follows the data. -- The error code follows the data.
p1_int_err_code <= vc_int_err_code when (live_1 and vc_int_data_strobe = '1') else p1_int_err_code <= vc_int_err_code when (live_1 and vc_int_data_strobe = '1') else
p1_int_err_code_latched; p1_int_err_code_latched;
...@@ -258,7 +258,7 @@ begin ...@@ -258,7 +258,7 @@ begin
process (clk) process (clk)
begin begin
if (rising_edge(clk)) then if (rising_edge(clk)) then
l_data <= vc_int_data_o; l_data <= vc_int_data_read;
l_err_code <= vc_int_err_code; l_err_code <= vc_int_err_code;
end if; end if;
end process; end process;
...@@ -292,19 +292,19 @@ begin ...@@ -292,19 +292,19 @@ begin
-- -- While client is live it data output tracks live data -- -- While client is live it data output tracks live data
-- psl live_track_1: -- psl live_track_1:
-- assert always {active_1; vc_int_data_strobe = '1'} -- assert always {active_1; vc_int_data_strobe = '1'}
-- |=> p1_int_data_o = vc_int_data_o -- |=> p1_int_data_read = vc_int_data_read
-- until vc_int_data_strobe = '0' or not live_1; -- until vc_int_data_strobe = '0' or not live_1;
-- psl live_track_2: -- psl live_track_2:
-- assert always {active_2; vc_int_data_strobe = '1'} -- assert always {active_2; vc_int_data_strobe = '1'}
-- |=> p2_int_data_o = vc_int_data_o -- |=> p2_int_data_read = vc_int_data_read
-- until vc_int_data_strobe = '0' or not live_2; -- until vc_int_data_strobe = '0' or not live_2;
-- -- If we sent p1_int_vme_go then the VME core will eventually receive it -- -- If we sent p1_int_vme_go then the VME core will eventually receive it
-- psl p1_vme_addr: assert always {p1_int_vme_go} -- psl p1_vme_addr: assert always {p1_int_vme_go}
-- |=> eventually! vc_int_addr = p1_int_addr ; -- |=> eventually! vc_int_addr = p1_int_addr ;
-- psl p1_vme_data_i: assert always {p1_int_vme_go} -- psl p1_vme_data_i: assert always {p1_int_vme_go}
-- |=> eventually! vc_int_data_i = p1_int_data_i ; -- |=> eventually! vc_int_data_write = p1_int_data_write ;
-- psl p1_vme_am_i: assert always {p1_int_vme_go} -- psl p1_vme_am_i: assert always {p1_int_vme_go}
-- |=> eventually! vc_int_am_i = p1_int_am_i ; -- |=> eventually! vc_int_am_i = p1_int_am_i ;
-- psl p1_vme_rw: assert always {p1_int_vme_go} -- psl p1_vme_rw: assert always {p1_int_vme_go}
...@@ -322,7 +322,7 @@ begin ...@@ -322,7 +322,7 @@ begin
-- psl p2_vme_addr: assert always {p2_int_vme_go} -- psl p2_vme_addr: assert always {p2_int_vme_go}
-- |=> eventually! vc_int_addr = p2_int_addr ; -- |=> eventually! vc_int_addr = p2_int_addr ;
-- psl p2_vme_data_i: assert always {p2_int_vme_go} -- psl p2_vme_data_i: assert always {p2_int_vme_go}
-- |=> eventually! vc_int_data_i = p2_int_data_i ; -- |=> eventually! vc_int_data_write = p2_int_data_write ;
-- psl p2_vme_am_i: assert always {p2_int_vme_go} -- psl p2_vme_am_i: assert always {p2_int_vme_go}
-- |=> eventually! vc_int_am_i = p2_int_am_i ; -- |=> eventually! vc_int_am_i = p2_int_am_i ;
-- psl p2_vme_rw: assert always {p2_int_vme_go} -- psl p2_vme_rw: assert always {p2_int_vme_go}
...@@ -360,12 +360,12 @@ begin ...@@ -360,12 +360,12 @@ begin
-- -- Latched data tracks input while active and strobed -- -- Latched data tracks input while active and strobed
-- psl p1_tracks_data: assert always -- psl p1_tracks_data: assert always
-- {active_1 and vc_busy = '1' and vc_int_data_strobe = '1'} -- {active_1 and vc_busy = '1' and vc_int_data_strobe = '1'}
-- |=> p1_int_data_o_latched = l_data -- |=> p1_int_data_read_latched = l_data
-- until vc_int_data_strobe = '0' or not active_1; -- until vc_int_data_strobe = '0' or not active_1;
-- psl p2_tracks_data: assert always -- psl p2_tracks_data: assert always
-- {active_2 and vc_busy = '1' and vc_int_data_strobe = '1'} -- {active_2 and vc_busy = '1' and vc_int_data_strobe = '1'}
-- |=> p2_int_data_o_latched = l_data -- |=> p2_int_data_read_latched = l_data
-- until vc_int_data_strobe = '0' or not active_2; -- until vc_int_data_strobe = '0' or not active_2;
-- -- Latched error tracks input while active and strobed -- -- Latched error tracks input while active and strobed
......
...@@ -29,14 +29,14 @@ entity vme_core_arb is ...@@ -29,14 +29,14 @@ entity vme_core_arb is
signal cli_busy : out std_logic := '0'; signal cli_busy : out std_logic := '0';
signal cli_int_data_o : out vme_vec_64_t; signal cli_int_data_read : out vme_vec_64_t;
signal cli_int_data_strobe : out std_logic := c_DATA_CLEAR; signal cli_int_data_strobe : out std_logic := c_DATA_CLEAR;
signal cli_int_go_consumed_strobe : out std_logic := '0'; signal cli_int_go_consumed_strobe : out std_logic := '0';
signal cli_int_blt_decision : out std_logic := '0'; signal cli_int_blt_decision : out std_logic := '0';
signal cli_int_err_code : out err_vec_t := C_ERR_OK; signal cli_int_err_code : out err_vec_t := C_ERR_OK;
signal cli_int_addr : in vme_addr_t; signal cli_int_addr : in vme_addr_t;
signal cli_int_data_i : in vme_vec_64_t; signal cli_int_data_write : in vme_vec_64_t;
signal cli_int_am_i : in am_vec_t; signal cli_int_am_i : in am_vec_t;
signal cli_int_vme_write : in std_logic; signal cli_int_vme_write : in std_logic;
signal cli_int_vme_go : in std_logic; signal cli_int_vme_go : in std_logic;
...@@ -50,14 +50,14 @@ entity vme_core_arb is ...@@ -50,14 +50,14 @@ entity vme_core_arb is
-- Directions inverted relative to the core. -- Directions inverted relative to the core.
signal vc1_busy : in std_logic := '0'; signal vc1_busy : in std_logic := '0';
signal vc1_int_data_o : in vme_vec_64_t; signal vc1_int_data_read : in vme_vec_64_t;
signal vc1_int_data_strobe : in std_logic := c_DATA_CLEAR; signal vc1_int_data_strobe : in std_logic := c_DATA_CLEAR;
signal vc1_int_go_consumed_strobe : in std_logic := '0'; signal vc1_int_go_consumed_strobe : in std_logic := '0';
signal vc1_int_blt_decision : in std_logic := '0'; signal vc1_int_blt_decision : in std_logic := '0';
signal vc1_int_err_code : in err_vec_t := C_ERR_OK; signal vc1_int_err_code : in err_vec_t := C_ERR_OK;
signal vc1_int_addr : out vme_addr_t; signal vc1_int_addr : out vme_addr_t;
signal vc1_int_data_i : out vme_vec_64_t; signal vc1_int_data_write : out vme_vec_64_t;
signal vc1_int_am_i : out am_vec_t; signal vc1_int_am_i : out am_vec_t;
signal vc1_int_vme_write : out std_logic; signal vc1_int_vme_write : out std_logic;
signal vc1_int_vme_go : out std_logic; signal vc1_int_vme_go : out std_logic;
...@@ -71,14 +71,14 @@ entity vme_core_arb is ...@@ -71,14 +71,14 @@ entity vme_core_arb is
-- Directions inverted relative to the core.