Propagate retzero

src/vme_cli_arb.vhd

@@ -40,6 +40,7 @@ entity vme_cli_arb is
     signal p1_int_blt_continue     : in std_logic;
 
     signal p1_int_berr_ok          : in std_logic;
+    signal p1_int_retzero          : in std_logic;    
 
     -- Signals to/from the second client.
 
@@ -62,6 +63,7 @@ entity vme_cli_arb is
     signal p2_int_blt_continue     : in std_logic;
 
     signal p2_int_berr_ok          : in std_logic;
+    signal p2_int_retzero          : in std_logic;        
 
     -- Signals to/from the VME core.
     -- Directions inverted relative to the core.
@@ -84,7 +86,8 @@ entity vme_cli_arb is
     signal vc_int_blt_decided      : out std_logic;
     signal vc_int_blt_continue     : out std_logic;
 
-    signal vc_int_berr_ok          : out std_logic
+    signal vc_int_berr_ok          : out std_logic;
+    signal vc_int_retzero          : out std_logic       
 
 --    -- Dropped signals (since they cannot be multiplexed /
 --    -- span multiple access cycles).
@@ -204,6 +207,7 @@ begin
   vc_int_blt_decided  <= p1_int_blt_decided   when live_1 else p2_int_blt_decided;
   vc_int_blt_continue <= p1_int_blt_continue  when live_1 else p2_int_blt_continue;
   vc_int_berr_ok      <= p1_int_berr_ok       when live_1 else p2_int_berr_ok;
+  vc_int_retzero      <= p1_int_retzero       when live_1 else p2_int_retzero;
 
   -- Signals to the clients from the VME core:
 

src/vme_core_arb.vhd

@@ -46,6 +46,7 @@ entity vme_core_arb is
     signal cli_int_blt_continue     : in std_logic;
 
     signal cli_int_berr_ok          : in std_logic;
+    signal cli_int_retzero          : in std_logic;        
 
     -- Signals to/from the first VME core.
     -- Directions inverted relative to the core.
@@ -68,6 +69,7 @@ entity vme_core_arb is
     signal vc1_int_blt_continue     : out std_logic;
 
     signal vc1_int_berr_ok          : out std_logic;
+    signal vc1_int_retzero          : out std_logic;            
 
     -- Signals to/from the second VME core.
     -- Directions inverted relative to the core.
@@ -89,7 +91,8 @@ entity vme_core_arb is
     signal vc2_int_blt_decided      : out std_logic;
     signal vc2_int_blt_continue     : out std_logic;
 
-    signal vc2_int_berr_ok          : out std_logic    
+    signal vc2_int_berr_ok          : out std_logic;
+    signal vc2_int_retzero          : out std_logic
     );
 end entity;
 
@@ -117,6 +120,7 @@ begin
   vc1_int_blt_decided    <= cli_int_blt_decided;
   vc1_int_blt_continue   <= cli_int_blt_continue;
   vc1_int_berr_ok        <= cli_int_berr_ok;
+  vc1_int_retzero        <= cli_int_retzero;
 
   vc2_int_addr           <= cli_int_addr;
   vc2_int_data_write         <= cli_int_data_write;
@@ -125,7 +129,7 @@ begin
   vc2_int_blt_decided    <= cli_int_blt_decided;
   vc2_int_blt_continue   <= cli_int_blt_continue;
   vc2_int_berr_ok        <= cli_int_berr_ok;
-
+  vc2_int_retzero        <= cli_int_retzero;
 
   G_AM_SELECT : if am_select generate
     core_1 <= cli_int_am_i /= am_magic;
@@ -135,7 +139,8 @@ begin
     addr_magic_slv <= std_logic_vector(to_unsigned(addr_magic, addr_magic_slv'length));
     
     core_1 <= addr_magic_slv /=
-              cli_int_addr(addr_magic_slv'high downto addr_magic_slv'low);
+              cli_int_addr(addr_magic_slv'high downto addr_magic_slv'low)
+              and cli_int_retzero = '0';
   end generate;
   
   vc1_int_vme_go <= '1' when cli_int_vme_go = '1' and core_1 else '0';