Merge branch 'master' of gitlab.au.dk:rimfaxe/vme_core

src/vme_data_bus.vhd

@@ -245,10 +245,9 @@ architecture rtl of vme_data_bus is
   signal l_addr_mode            : addr_type_t;
   signal l_transfer_mode        : transfer_type_t;
 
-  -- Latched data
-  -- If READ_OP it stores the data read from slave.
-  -- If WRITE_OP it stores the data to write to slave.
-  signal l_data             : std_logic_vector(63 downto 0) := (others => '0');
+  -- Latched data, separate for write and read directions.
+  signal l_data_r           : std_logic_vector(63 downto 0) := (others => '0');
+  signal l_data_w           : std_logic_vector(63 downto 0) := (others => '0');
 
   signal first_cycle                  : std_logic := '1';
 
@@ -350,7 +349,7 @@ begin
               -- D32 |                                    B(0)     B(1)     B(2)   B(3)
               -- D64 |   B(0)     B(1)     B(2)   B(3)    B(4)     B(5)     B(6)   B(7)
               l_addr <= int_addr;              
-              l_data <= int_data_write;
+              l_data_w <= int_data_write;
               l_am <= int_am_i;
               l_rw <= int_vme_write;
               l_transfer_mode <= transfer_mode;
@@ -425,7 +424,7 @@ begin
                 else
                   -- Still in addressing phase.
                   -- We can only place data on D lines
-                  vme_data_o <= l_data(31 downto 0);
+                  vme_data_o <= l_data_w(31 downto 0);
                   vme_data_dir <= c_PIN_OUT;
 
                   -- Rule 2.34a
@@ -456,9 +455,9 @@ begin
               end if;              
             else
               -- Write cycle. Place data and wait
-              vme_data_o <= l_data(31 downto 0);
+              vme_data_o <= l_data_w(31 downto 0);
               if (l_transfer_mode = MBLT) then
-                vme_addr_o <= l_data(63 downto 32);
+                vme_addr_o <= l_data_w(63 downto 32);
               end if;
               vme_data_dir <= c_PIN_OUT;
 
@@ -572,27 +571,33 @@ begin
           -- Conclusion:
           -- The D lines always carry the least significant bits.
           -- If we run MBLT then the A lines with carry the MSB.
-          -- 
-          cur_data(31 downto 0) := vme_data_i;
+          cur_data(15 downto 0) := vme_data_i;
+          if (l_addr[0] = '0' or l_transfer_mode = MBLT) then
+            cur_data(31 downto 16) := vme_data_i;
+          else
+            cur_data(31 downto 16) := (others => '0');
+          end if;
           case l_transfer_mode is
             when SINGLE | BLT =>
-              -- l_data(31 downto 0) => vme_data_i;
+              -- l_data_r(31 downto 0) => vme_data_i;
               cur_data(63 downto 32) := (others => '0');
             when MBLT =>
-              -- l_data(31 downto 0) => vme_addr_i;
+              -- l_data_r(31 downto 0) => vme_addr_i;
               cur_data(63 downto 32) := vme_addr_i;
             when others =>
               assert false report "Logic error!";
           end case;
           
-          -- Munk: In principle we can have cur_data = l_data,
+          -- Munk: In principle we can have cur_data = l_data_r,
           -- first time n_wait = 0.
-          -- In this case l_data is latched when n_wait = 1.
+          -- In this case l_data_r is latched when n_wait = 1.
           -- Howver, according to observation 2.47a, then data is
           -- valid WITHIN 25ns. 
           if (n_wait = 0) then
-            -- Latched data stable
-            if (cur_data = l_data) then
+            -- Latched data stable; only check used bits
+            if (cur_data(31 downto 0) = l_data_r(31 downto 0) and
+                (transfer_mode /= MBLT or
+                 cur_data(63 downto 32) = l_data_r(63 downto 32))) then
               -- Slave only maintains data lines while
               -- DS* asserted. They can be deasserted now. 
               vme_ds_n_o <= "11";
@@ -618,14 +623,14 @@ begin
               n_wait <= 1;
             end if;
           end if;
-          l_data <= cur_data;
+          l_data_r <= cur_data;
 
         when BLT_WRITE_WAIT =>
           if int_blt_decided = '1' then
             int_blt_decision <= '0';
             
             if int_blt_continue = '1' then
-              l_data <= int_data_write; -- Latch new data
+              l_data_w <= int_data_write; -- Latch new data
               state <= DTACK_HIGH_WAIT; -- Wait for slave to rescind DTACK
             else
               -- Terminate cycle
@@ -837,7 +842,7 @@ begin
     --   assert always {state = IDLE and int_vme_go = '1'
     --                  and transfer_mode /= TRANSFER_ERR
     --                  and addr_mode /= ADDR_ERR}
-    --     |=> l_data = f_data;    
+    --     |=> l_data_w = f_data;    
 
     -- -- Maintain BUSY until back in IDLE
     -- psl core_is_busy_until_idle:
@@ -904,7 +909,7 @@ begin
     --   assert always {l_transfer_mode = SINGLE
     --                  and l_rw = c_VME_WRITE
     --                  and state = DTACK_HIGH_WAIT; vme_dtack_n_i = '1'}
-    --     |=> vme_data_o = l_data(31 downto 0);
+    --     |=> vme_data_o = l_data_w(31 downto 0);
 
     -- -- If IDLE and GO given
     -- -- and data lines are free (DTACK* = 1)
@@ -914,7 +919,7 @@ begin
     --   assert always {int_vme_go = '1' and state = IDLE
     --                  and int_vme_write = c_VME_WRITE and vme_dtack_n_i = '1'
     --                  and int_am_i = c_AM_A24_DATA}
-    --     |=> vme_data_o = l_data(31 downto 0)
+    --     |=> vme_data_o = l_data_w(31 downto 0)
     --     until state = DTACK_LOW_WAIT or state = IDLE;
 
     -- -- When writing MBLT the data will be placed on the bus
@@ -922,8 +927,8 @@ begin
     --   assert always {state = DTACK_HIGH_WAIT and l_transfer_mode = MBLT
     --                  and first_cycle = '1' and vme_dtack_n_i = '1'
     --                  and l_rw = c_VME_WRITE}
-    --     |=> vme_data_o = l_data(31 downto 0)
-    --     and vme_addr_o = l_data(63 downto 32);
+    --     |=> vme_data_o = l_data_w(31 downto 0)
+    --     and vme_addr_o = l_data_w(63 downto 32);
 
     -- -- When writing MBLT the data latched during BLT_WRITE_WAIT
     -- -- is written to both addr and data pins
@@ -954,8 +959,8 @@ begin
     -- psl data_is_latched_when_stable:
     --   assert always {state = LATCH_DATA and n_wait = 0
     --                  and f_latch_data = f_latch_data2 and l_transfer_mode /= MBLT}
-    --     |-> l_data(31 downto 0) = f_latch_data(31 downto 0)
-    --     and l_data(63 downto 32) = "00000000000000000000000000000000";
+    --     |-> l_data_r(31 downto 0) = f_latch_data(31 downto 0)
+    --     and l_data_r(63 downto 32) = "00000000000000000000000000000000";
 
     -- -- When latching 64 bit data,
     -- -- then low 32 bits are from data lines
@@ -964,8 +969,8 @@ begin
     --   assert always {state = LATCH_DATA
     --                  and f_latch_data = f_latch_data2 and l_transfer_mode = MBLT;
     --                  n_wait = 0}
-    --     |-> l_data(31 downto 0) = f_latch_data(31 downto 0)
-    --     and l_data(63 downto 32) = f_latch_data(63 downto 32); 
+    --     |-> l_data_r(31 downto 0) = f_latch_data(31 downto 0)
+    --     and l_data_r(63 downto 32) = f_latch_data(63 downto 32); 
     
 
     -- -- If BLT write is continued,
@@ -973,7 +978,7 @@ begin
     -- psl if_continueing_blt_write_then_latch_new_data:
     --   assert always {state = BLT_WRITE_WAIT
     --                  and int_blt_decided = '1' and int_blt_continue = '1'}
-    --     |=> l_data = f_blt_data;    
+    --     |=> l_data_w = f_blt_data;    
     
 
   end generate FormalG;