Commit 7dd2a905 authored by Håkan Johansson's avatar Håkan Johansson
Browse files

Latch the signals. Need to be declared.

parent 288475ce
Pipeline #13923 failed with stage
in 14 seconds
......@@ -158,6 +158,18 @@ begin
prefer_1 <= true;
end if;
-- We select on active instead of live, since active is cheaper (comes
-- directly from a flip-flop, instead of logic), and
-- vc_int_data_strobe will not come on the first cycle.
if (active_1 and vc_int_data_strobe) then
p1_int_data_o_latched <= vc_int_data_o;
p1_int_err_code_latched <= vc_int_err_code;
end if;
if (active_2 and vc_int_data_strobe) then
p2_int_data_o_latched <= vc_int_data_o;
p2_int_err_code_latched <= vc_int_err_code;
end if;
end if;
end process;
......@@ -179,6 +191,10 @@ begin
-- Signals to the clients from the VME core:
-- TODO: All the selects below could use active_1 / active_2 instead
-- of live_1 / live_2, since the signals from the VME core
-- will not happen on the first cycle we are active!
-- Data is passed directly through on the cycle they have been latched.
-- Otherwise, take the latched value:
p1_int_data_o <= vc_int_data_o when (live_1 and vc_int_data_strobe) else
......
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