Commit 7512196c authored by Michael Munch's avatar Michael Munch
Browse files

blt_decision_strobe => blt_decision

parent 97babfa8
Pipeline #25606 failed with stage
in 22 seconds
......@@ -22,7 +22,7 @@ architecture tb of tb_vme_bus is
signal p1_int_data_o : vme_vec_64_t;
signal p1_int_data_strobe : std_logic := c_DATA_CLEAR;
signal p1_int_go_consumed_strobe : std_logic := '0';
signal p1_int_blt_decision_strobe : std_logic := '0';
signal p1_int_blt_decision : std_logic := '0';
signal p1_int_err_code : err_vec_t := C_ERR_OK;
signal p1_int_addr : vme_addr_t;
......@@ -43,7 +43,7 @@ architecture tb of tb_vme_bus is
signal p2_int_data_o : vme_vec_64_t;
signal p2_int_data_strobe : std_logic := c_DATA_CLEAR;
signal p2_int_go_consumed_strobe : std_logic := '0';
signal p2_int_blt_decision_strobe : std_logic := '0';
signal p2_int_blt_decision : std_logic := '0';
signal p2_int_err_code : err_vec_t := C_ERR_OK;
signal p2_int_addr : vme_addr_t;
......@@ -66,7 +66,7 @@ architecture tb of tb_vme_bus is
signal vc1_int_data_o : vme_vec_64_t;
signal vc1_int_data_strobe : std_logic := c_DATA_CLEAR;
signal vc1_int_go_consumed_strobe : std_logic := '0';
signal vc1_int_blt_decision_strobe : std_logic := '0';
signal vc1_int_blt_decision : std_logic := '0';
signal vc1_int_err_code : err_vec_t := C_ERR_OK;
signal vc1_int_addr : vme_addr_t;
......@@ -87,7 +87,7 @@ architecture tb of tb_vme_bus is
signal vc2_int_data_o : vme_vec_64_t;
signal vc2_int_data_strobe : std_logic := c_DATA_CLEAR;
signal vc2_int_go_consumed_strobe : std_logic := '0';
signal vc2_int_blt_decision_strobe : std_logic := '0';
signal vc2_int_blt_decision : std_logic := '0';
signal vc2_int_err_code : err_vec_t := C_ERR_OK;
signal vc2_int_addr : vme_addr_t;
......@@ -150,7 +150,7 @@ begin
p1_int_data_o => p1_int_data_o,
p1_int_data_strobe => p1_int_data_strobe,
p1_int_go_consumed_strobe => p1_int_go_consumed_strobe,
p1_int_blt_decision_strobe => p1_int_blt_decision_strobe,
p1_int_blt_decision => p1_int_blt_decision,
p1_int_err_code => p1_int_err_code,
p1_int_addr => p1_int_addr,
......@@ -171,7 +171,7 @@ begin
p2_int_data_o => p2_int_data_o,
p2_int_data_strobe => p2_int_data_strobe,
p2_int_go_consumed_strobe => p2_int_go_consumed_strobe,
p2_int_blt_decision_strobe => p2_int_blt_decision_strobe,
p2_int_blt_decision => p2_int_blt_decision,
p2_int_err_code => p2_int_err_code,
p2_int_addr => p2_int_addr,
......@@ -191,7 +191,7 @@ begin
vc1_int_data_o => vc1_int_data_o,
vc1_int_data_strobe => vc1_int_data_strobe,
vc1_int_go_consumed_strobe => vc1_int_go_consumed_strobe,
vc1_int_blt_decision_strobe => vc1_int_blt_decision_strobe,
vc1_int_blt_decision => vc1_int_blt_decision,
vc1_int_err_code => vc1_int_err_code,
vc1_int_addr => vc1_int_addr,
......@@ -212,7 +212,7 @@ begin
vc2_int_data_o => vc2_int_data_o,
vc2_int_data_strobe => vc2_int_data_strobe,
vc2_int_go_consumed_strobe => vc2_int_go_consumed_strobe,
vc2_int_blt_decision_strobe => vc2_int_blt_decision_strobe,
vc2_int_blt_decision => vc2_int_blt_decision,
vc2_int_err_code => vc2_int_err_code,
vc2_int_addr => vc2_int_addr,
......
......@@ -26,7 +26,7 @@ entity vme_cli_arb is
signal p1_int_data_o : out vme_vec_64_t;
signal p1_int_data_strobe : out std_logic := c_DATA_CLEAR;
signal p1_int_go_consumed_strobe : out std_logic := '0';
signal p1_int_blt_decision_strobe : out std_logic := '0';
signal p1_int_blt_decision : out std_logic := '0';
signal p1_int_err_code : out err_vec_t := C_ERR_OK;
signal p1_int_addr : in vme_addr_t;
......@@ -47,7 +47,7 @@ entity vme_cli_arb is
signal p2_int_data_o : out vme_vec_64_t;
signal p2_int_data_strobe : out std_logic := c_DATA_CLEAR;
signal p2_int_go_consumed_strobe : out std_logic := '0';
signal p2_int_blt_decision_strobe : out std_logic := '0';
signal p2_int_blt_decision : out std_logic := '0';
signal p2_int_err_code : out err_vec_t := C_ERR_OK;
signal p2_int_addr : in vme_addr_t;
......@@ -69,7 +69,7 @@ entity vme_cli_arb is
signal vc_int_data_o : in vme_vec_64_t;
signal vc_int_data_strobe : in std_logic := c_DATA_CLEAR;
signal vc_int_go_consumed_strobe : in std_logic := '0';
signal vc_int_blt_decision_strobe : in std_logic := '0';
signal vc_int_blt_decision : in std_logic := '0';
signal vc_int_err_code : in err_vec_t := C_ERR_OK;
signal vc_int_addr : out vme_addr_t;
......@@ -232,8 +232,8 @@ begin
p1_int_go_consumed_strobe <= vc_int_go_consumed_strobe when live_1 else '0';
p2_int_go_consumed_strobe <= vc_int_go_consumed_strobe when live_2 else '0';
p1_int_blt_decision_strobe <= vc_int_blt_decision_strobe when live_1 else '0';
p2_int_blt_decision_strobe <= vc_int_blt_decision_strobe when live_2 else '0';
p1_int_blt_decision <= vc_int_blt_decision when live_1 else '0';
p2_int_blt_decision <= vc_int_blt_decision when live_2 else '0';
-- The busy of a client is simply while it is live.
-- This actually means that we will report busy some cycles
......@@ -352,10 +352,10 @@ begin
-- -- BLT decision strobes are routed to live client
-- psl p1_get_blt_strobe: assert always {live_1}
-- |=> p1_int_blt_decision_strobe = vc_int_blt_decision_strobe until not live_1;
-- |=> p1_int_blt_decision = vc_int_blt_decision until not live_1;
-- psl p2_get_blt_strobe: assert always {live_2}
-- |=> p2_int_blt_decision_strobe = vc_int_blt_decision_strobe until not live_2;
-- |=> p2_int_blt_decision = vc_int_blt_decision until not live_2;
-- -- Latched data tracks input while active and strobed
-- psl p1_tracks_data: assert always
......
......@@ -32,7 +32,7 @@ entity vme_core_arb is
signal cli_int_data_o : out vme_vec_64_t;
signal cli_int_data_strobe : out std_logic := c_DATA_CLEAR;
signal cli_int_go_consumed_strobe : out std_logic := '0';
signal cli_int_blt_decision_strobe : out std_logic := '0';
signal cli_int_blt_decision : out std_logic := '0';
signal cli_int_err_code : out err_vec_t := C_ERR_OK;
signal cli_int_addr : in vme_addr_t;
......@@ -53,7 +53,7 @@ entity vme_core_arb is
signal vc1_int_data_o : in vme_vec_64_t;
signal vc1_int_data_strobe : in std_logic := c_DATA_CLEAR;
signal vc1_int_go_consumed_strobe : in std_logic := '0';
signal vc1_int_blt_decision_strobe : in std_logic := '0';
signal vc1_int_blt_decision : in std_logic := '0';
signal vc1_int_err_code : in err_vec_t := C_ERR_OK;
signal vc1_int_addr : out vme_addr_t;
......@@ -74,7 +74,7 @@ entity vme_core_arb is
signal vc2_int_data_o : in vme_vec_64_t;
signal vc2_int_data_strobe : in std_logic := c_DATA_CLEAR;
signal vc2_int_go_consumed_strobe : in std_logic := '0';
signal vc2_int_blt_decision_strobe : in std_logic := '0';
signal vc2_int_blt_decision : in std_logic := '0';
signal vc2_int_err_code : in err_vec_t := C_ERR_OK;
signal vc2_int_addr : out vme_addr_t;
......@@ -100,7 +100,7 @@ begin
-- cli_busy <= '1' when vc1_busy = '1' or vc2_busy = '1' else '0';
cli_busy <= vc1_busy or vc2_busy ;
cli_int_data_strobe <= vc1_int_go_consumed_strobe or vc2_int_go_consumed_strobe ;
cli_int_blt_decision_strobe <= vc1_int_blt_decision_strobe or vc2_int_blt_decision_strobe;
cli_int_blt_decision <= vc1_int_blt_decision or vc2_int_blt_decision;
cli_int_go_consumed_strobe <= vc1_int_go_consumed_strobe or vc2_int_go_consumed_strobe ;
cli_int_data_o <= vc1_int_data_o when core_1 else vc2_int_data_o;
......
......@@ -163,7 +163,7 @@ entity vme_data_bus is
-- Strobe that indicates when a BLT decision is needed.
-- See int_blt_decided and int_blt_continue
signal int_blt_decision_strobe : out std_logic := '0';
signal int_blt_decision : out std_logic := '0';
-- Error code.
-- Consult vme_pkg.ERR_CODE for valid values.
......@@ -518,12 +518,12 @@ begin
when BLT =>
-- Per Rule 2.34a there must be 40ns delay
-- between DS* transistions. Handle this in next cycle
int_blt_decision_strobe <= '1';
int_blt_decision <= '1';
int_data_strobe <= c_DATA_PRESENT;
state <= BLT_WRITE_WAIT;
when MBLT =>
if first_cycle = '0' then
int_blt_decision_strobe <= '1';
int_blt_decision <= '1';
int_data_strobe <= c_DATA_PRESENT;
state <= BLT_WRITE_WAIT;
else
......@@ -598,7 +598,7 @@ begin
int_err_code <= c_ERR_OK;
when BLT | MBLT =>
n_wait <= c_N_DS_SPACING;
int_blt_decision_strobe <= '1';
int_blt_decision <= '1';
state <= BLT_READ_WAIT;
when others =>
assert false report "Logic error!";
......@@ -612,7 +612,7 @@ begin
when BLT_WRITE_WAIT =>
int_data_strobe <= c_DATA_CLEAR;
if int_blt_decided = '1' then
int_blt_decision_strobe <= '0';
int_blt_decision <= '0';
if int_blt_continue = '1' then
l_data <= int_data_i; -- Latch new data
......@@ -629,7 +629,7 @@ begin
when BLT_READ_WAIT =>
int_data_strobe <= c_DATA_CLEAR;
if int_blt_decided = '1' then
int_blt_decision_strobe <= '0';
int_blt_decision <= '0';
if int_blt_continue = '1' then
state <= DTACK_HIGH_WAIT;
else
......
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