Commit 54d8c5da authored by Michael Munch's avatar Michael Munch
Browse files

Removed redudant go flag

parent b46e86dd
Pipeline #15950 passed with stage
in 39 seconds
......@@ -39,8 +39,6 @@ entity vme_cli_arb is
signal p1_int_berr_ok : in std_logic;
signal p1_go : in std_logic;
-- Signals to/from the second client.
signal p2_busy : out std_logic := '0';
......@@ -62,8 +60,6 @@ entity vme_cli_arb is
signal p2_int_berr_ok : in std_logic;
signal p2_go : in std_logic;
-- Signals to/from the VME core.
-- Directions inverted relative to the core.
......@@ -142,8 +138,8 @@ architecture rtl of vme_cli_arb is
signal p2_int_err_code_latched : err_vec_t := C_ERR_OK;
begin
want_1 <= (p1_go = '1' and p2_go = '0') or (p1_go = '1' and prefer_1);
want_2 <= (p2_go = '1' and p1_go = '0') or (p2_go = '1' and not prefer_1);
want_1 <= (p1_int_vme_go = '1' and p2_int_vme_go = '0') or (p1_int_vme_go = '1' and prefer_1);
want_2 <= (p2_int_vme_go = '1' and p1_int_vme_go = '0') or (p2_int_vme_go = '1' and not prefer_1);
start_1 <= vc_busy = '0' and want_1;
start_2 <= vc_busy = '0' and want_2;
......@@ -277,11 +273,11 @@ begin
-- -- If both clients request access then we pick our favourite
-- psl pick_pref_client_1: assert always
-- {p1_go = '1' and p2_go = '1' and not prefer_1 and vc_busy = '0'}
-- {p1_int_vme_go = '1' and p2_int_vme_go = '1' and not prefer_1 and vc_busy = '0'}
-- |=> start_2 until active_2;
-- psl pick_pref_client_2: assert always
-- {p1_go = '1' and p2_go = '1' and prefer_1 and vc_busy = '0'}
-- {p1_int_vme_go = '1' and p2_int_vme_go = '1' and prefer_1 and vc_busy = '0'}
-- |=> start_1 until active_1;
-- -- While client is live it data output tracks live data
......@@ -295,40 +291,40 @@ begin
-- |=> p2_int_data_o = vc_int_data_o
-- until vc_int_data_strobe = '0' or not live_2;
-- -- If we sent p1_go then the VME core will eventually receive it
-- psl p1_vme_addr: assert always {p1_go}
-- -- If we sent p1_int_vme_go then the VME core will eventually receive it
-- psl p1_vme_addr: assert always {p1_int_vme_go}
-- |=> eventually! vc_int_addr = p1_int_addr ;
-- psl p1_vme_data_i: assert always {p1_go}
-- psl p1_vme_data_i: assert always {p1_int_vme_go}
-- |=> eventually! vc_int_data_i = p1_int_data_i ;
-- psl p1_vme_am_i: assert always {p1_go}
-- psl p1_vme_am_i: assert always {p1_int_vme_go}
-- |=> eventually! vc_int_am_i = p1_int_am_i ;
-- psl p1_vme_rw: assert always {p1_go}
-- psl p1_vme_rw: assert always {p1_int_vme_go}
-- |=> eventually! vc_int_vme_rw = p1_int_vme_rw ;
-- psl p1_vme_go: assert always {p1_go}
-- psl p1_vme_go: assert always {p1_int_vme_go}
-- |=> eventually! vc_int_vme_go = p1_int_vme_go ;
-- psl p1_vme_blt_deci: assert always {p1_go}
-- psl p1_vme_blt_deci: assert always {p1_int_vme_go}
-- |=> eventually! vc_int_blt_decided = p1_int_blt_decided ;
-- psl p1_vme_blt_cont: assert always {p1_go}
-- psl p1_vme_blt_cont: assert always {p1_int_vme_go}
-- |=> eventually! vc_int_blt_continue = p1_int_blt_continue ;
-- psl p1_vme_berr_ok: assert always {p1_go}
-- psl p1_vme_berr_ok: assert always {p1_int_vme_go}
-- |=> eventually! vc_int_berr_ok = p1_int_berr_ok ;
-- -- If we sent p2_go then the VME core will eventually receive it
-- psl p2_vme_addr: assert always {p2_go}
-- -- If we sent p2_int_vme_go then the VME core will eventually receive it
-- psl p2_vme_addr: assert always {p2_int_vme_go}
-- |=> eventually! vc_int_addr = p2_int_addr ;
-- psl p2_vme_data_i: assert always {p2_go}
-- psl p2_vme_data_i: assert always {p2_int_vme_go}
-- |=> eventually! vc_int_data_i = p2_int_data_i ;
-- psl p2_vme_am_i: assert always {p2_go}
-- psl p2_vme_am_i: assert always {p2_int_vme_go}
-- |=> eventually! vc_int_am_i = p2_int_am_i ;
-- psl p2_vme_rw: assert always {p2_go}
-- psl p2_vme_rw: assert always {p2_int_vme_go}
-- |=> eventually! vc_int_vme_rw = p2_int_vme_rw ;
-- psl p2_vme_go: assert always {p2_go}
-- psl p2_vme_go: assert always {p2_int_vme_go}
-- |=> eventually! vc_int_vme_go = p2_int_vme_go ;
-- psl p2_vme_blt_deci: assert always {p2_go}
-- psl p2_vme_blt_deci: assert always {p2_int_vme_go}
-- |=> eventually! vc_int_blt_decided = p2_int_blt_decided ;
-- psl p2_vme_blt_cont: assert always {p2_go}
-- psl p2_vme_blt_cont: assert always {p2_int_vme_go}
-- |=> eventually! vc_int_blt_continue = p2_int_blt_continue ;
-- psl p2_vme_berr_ok: assert always {p2_go}
-- psl p2_vme_berr_ok: assert always {p2_int_vme_go}
-- |=> eventually! vc_int_berr_ok = p2_int_berr_ok ;
-- -- Data strobes are routed to live client
......
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