Commit 43be3f36 authored by Michael Munch's avatar Michael Munch
Browse files

Move handling or Bus Request enable and dir to separate module

parent 1235dcd3
Pipeline #15918 failed with stage
in 17 seconds
......@@ -4,3 +4,4 @@ vme_bus
vme_bus_arb
vme_data_bus
octave-workspace
vme_bus_arb_phy
vunit arb_test (vme_bus_arb_phy(rtl))
{
stay_in_idle_until_br_received:
assert always true |=> vme_br_n_oe_n = c_OE_ON;
}
......@@ -12,7 +12,7 @@ entity vme_bus_arb is
signal vme_br_n_i : in std_logic_vector(3 downto 0);
signal vme_bgin_n_i : in std_logic_vector(3 downto 0);
signal vme_bgout_n_o : out std_logic_vector(3 downto 0) => (others => '1');
signal vme_bgout_n_o : out std_logic_vector(3 downto 0) := (others => '1');
signal vme_bbsy_n_i : in std_logic;
signal vme_bclr_n_o : out std_logic := '1'
......
[options]
mode bmc
depth 20
[engines]
smtbmc z3
[script]
ghdl -fpsl --std=08 -gformal=true vme_pkg.vhd vme_bus_arb_phy.vhd formal_vme_bus_arb_phy.vhd -e vme_bus_arb_phy
prep -top vme_bus_arb_phy
[files]
vme_bus_arb_phy.vhd
vme_pkg.vhd
test/formal_vme_bus_arb_phy.vhd
\ No newline at end of file
library ieee;
use ieee.std_logic_1164.all;
use work.vme_pkg.all;
entity vme_bus_arb_phy is
port (
signal vme_br_n_i : in std_logic_vector(3 downto 0);
signal vme_br_n_dir : out std_logic := c_PIN_IN;
signal vme_br_n_oe_n : out std_logic := c_OE_ON;
signal vme_bgin_n_i : in std_logic_vector(3 downto 0);
signal vme_bgin_n_oe_n : out std_logic := c_OE_ON;
signal vme_bgout_n_oe_n : out std_logic := c_OE_ON;
signal vme_bbsy_n_i : in std_logic;
signal vme_bbsy_n_dir : out std_logic := c_PIN_IN;
signal vme_bclr_n_i : in std_logic;
signal vme_bclr_n_dir : out std_logic := c_PIN_IN;
signal br_n_o : out std_logic_vector(3 downto 0) := (others => '1');
signal bgin_n_o : out std_logic_vector(3 downto 0) := (others => '1');
signal bgout_n_o : out std_logic_vector(3 downto 0) := (others => '1');
signal bbsy_n_o : out std_logic := '1';
signal bclr_n_o : out std_logic := '1';
signal int_br_n_i : in std_logic_vector(3 downto 0);
signal int_bbsy_n_i : in std_logic := '1';
signal int_bclr_n_i : in std_logic := '1';
signal int_bgout_n_i : in std_logic_vector(3 downto 0)
);
end entity;
architecture rtl of vme_bus_arb_phy is
signal has_no_int_breq : std_logic;
signal has_no_int_bbsy : std_logic;
signal has_no_int_bclr : std_logic;
begin
-- Always enable signals
vme_br_n_oe_n <= c_OE_ON;
vme_bgout_n_oe_n <= c_OE_ON;
vme_bgin_n_oe_n <= c_OE_ON;
-- BR, BBSY and BCLR are all active low
has_no_int_bbsy <= int_bbsy_n_i;
has_no_int_bclr <= int_bclr_n_i;
has_no_int_breq <= and int_br_n_i;
-- If internal signals not active => Pins are input
vme_bbsy_n_dir <= c_PIN_IN when has_no_int_bbsy else c_PIN_OUT;
vme_bclr_n_dir <= c_PIN_IN when has_no_int_bclr else c_PIN_OUT;
vme_br_n_dir <= c_PIN_IN when has_no_int_breq else c_PIN_OUT;
-- If internal signals not active => Backplane signals propagated.
bbsy_n_o <= vme_bbsy_n_i when has_no_int_bbsy else '0';
bclr_n_o <= vme_bclr_n_i when has_no_int_bclr else '0';
br_n_o <= vme_br_n_i when has_no_int_breq else int_br_n_i;
-- Simply propagate internal bus grants
vme_bgout_n_o <= int_bgout_n_i;
bgin_n_o <= vme_bgin_n_i;
end architecture;
\ No newline at end of file
......@@ -120,9 +120,9 @@ entity vme_data_bus is
-- Receive bus grant
signal vme_bgin_n_i : in std_logic_vector(3 downto 0);
-- Output bus grant
-- signal vme_bgout_n_o : out std_logic_vector(3 downto 0);
signal vme_bgout_n_o : out std_logic_vector(3 downto 0);
-- Signal bus ownership
-- signal vme_bbsy_n_o : out std_logic;
signal vme_bbsy_n_o : out std_logic;
-- Signal the we should clear bus
signal vme_bclr_n_i : in std_logic;
......
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