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Commit 2fdc70f0 authored by Michael Munch's avatar Michael Munch
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VME data bus tb fix

parent 704c126d
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run.py
View file @ 2fdc70f0
......@@ -15,5 +15,5 @@ ui.enable_location_preprocessing()
ui.add_array_util()
lib = ui.add_library("vme")
lib.add_source_files(join(root, "src", "*.vhd"))
lib.add_source_files(join(root, "src", "test", "tb_vme_cli_arb.vhd"))
lib.add_source_files(join(root, "src", "test", "*.vhd"))
ui.main()
src/test/tb_vme_bus.vhd
View file @ 2fdc70f0
......@@ -153,6 +153,7 @@ begin
vme_dtack_n_i <= '1';
vme_berr_n_i <= '1';
int_vme_go <= '1';
int_vme_rw <= c_VME_READ;
int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '1');
......@@ -690,31 +691,6 @@ begin
check_equal(vme_data_o, unsigned'(B"11111111111111111111111111111111"));
check_equal(vme_addr_o, unsigned'(B"11111111111111111111111111111111"));
elsif run("if int_berr_ok = false and BERR is received => ERR") then
vme_dtack_n_i <= '1';
vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ;
int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '1');
vme_data_i <= (others => '1');
wait for 20 ns;
check_equal(vme_addr_dir, c_PIN_OUT);
check_equal(vme_am_dir, c_PIN_OUT);
check_equal(vme_iack_n_dir, c_PIN_OUT);
check_equal(vme_addr_o, int_addr);
check_equal(vme_as_n_dir, c_PIN_IN);
wait for 40 ns;
check_equal(vme_ds_n_dir, c_PIN_OUT);
check_equal(vme_ds_n_o, unsigned'(B"00"));
vme_berr_n_i <= '0';
wait for 10 ns;
check_equal(int_err_code, c_ERR_BERR);
elsif run("if doing BLT write then data is placed on data lines") then
vme_dtack_n_i <= '1';
......@@ -920,6 +896,6 @@ begin
int_blt_decided => int_blt_decided,
int_blt_continue => int_blt_continue,
int_timeout_n => '0'
int_timeout_n => '1'
);
end architecture;
src/test/tb_vme_cli_arb.vhd deleted 100644 → 0
View file @ 704c126d
library vunit_lib;
context vunit_lib.vunit_context;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme_pkg.all;
entity tb_vme_bus is
generic (runner_cfg : string);
end entity;
architecture tb of tb_vme_bus is
signal clk : std_logic := '0';
-- Signals to/from the first client.
-- For documentation on the signal purposes, see vme_bus.vhd.
signal p1_busy : std_logic := '0';
signal p1_int_data_o : vme_vec_64_t;
signal p1_int_data_strobe : std_logic := c_DATA_CLEAR;
signal p1_int_go_consumed_strobe : std_logic := '0';
signal p1_int_blt_decision : std_logic := '0';
signal p1_int_err_code : err_vec_t := C_ERR_OK;
signal p1_int_addr : vme_addr_t;
signal p1_int_data_i : vme_vec_64_t;
signal p1_int_am_i : am_vec_t;
signal p1_int_vme_rw : std_logic := '0';
signal p1_int_vme_go : std_logic := '0';
signal p1_int_blt_decided : std_logic;
signal p1_int_blt_continue : std_logic;
signal p1_int_berr_ok : std_logic;
-- Signals to/from the second client.
signal p2_busy : std_logic := '0';
signal p2_int_data_o : vme_vec_64_t;
signal p2_int_data_strobe : std_logic := c_DATA_CLEAR;
signal p2_int_go_consumed_strobe : std_logic := '0';
signal p2_int_blt_decision : std_logic := '0';
signal p2_int_err_code : err_vec_t := C_ERR_OK;
signal p2_int_addr : vme_addr_t;
signal p2_int_data_i : vme_vec_64_t;
signal p2_int_am_i : am_vec_t;
signal p2_int_vme_rw : std_logic := '0';
signal p2_int_vme_go : std_logic := '0';
signal p2_int_blt_decided : std_logic;
signal p2_int_blt_continue : std_logic;
signal p2_int_berr_ok : std_logic;
-- Signals to/from the VME core.
-- Directions inverted relative to the core.
-- Core 1
signal vc1_busy : std_logic := '0';
signal vc1_int_data_o : vme_vec_64_t;
signal vc1_int_data_strobe : std_logic := c_DATA_CLEAR;
signal vc1_int_go_consumed_strobe : std_logic := '0';
signal vc1_int_blt_decision : std_logic := '0';
signal vc1_int_err_code : err_vec_t := C_ERR_OK;
signal vc1_int_addr : vme_addr_t;
signal vc1_int_data_i : vme_vec_64_t;
signal vc1_int_am_i : am_vec_t;
signal vc1_int_vme_rw : std_logic;
signal vc1_int_vme_go : std_logic;
signal vc1_int_blt_decided : std_logic;
signal vc1_int_blt_continue : std_logic;
signal vc1_int_berr_ok : std_logic;
-- Core 2
signal vc2_busy : std_logic := '0';
signal vc2_int_data_o : vme_vec_64_t;
signal vc2_int_data_strobe : std_logic := c_DATA_CLEAR;
signal vc2_int_go_consumed_strobe : std_logic := '0';
signal vc2_int_blt_decision : std_logic := '0';
signal vc2_int_err_code : err_vec_t := C_ERR_OK;
signal vc2_int_addr : vme_addr_t;
signal vc2_int_data_i : vme_vec_64_t;
signal vc2_int_am_i : am_vec_t;
signal vc2_int_vme_rw : std_logic;
signal vc2_int_vme_go : std_logic;
signal vc2_int_blt_decided : std_logic;
signal vc2_int_blt_continue : std_logic;
signal vc2_int_berr_ok : std_logic;
begin
main: process
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("p1 read with AM=0x39 is directed to core 1") then
wait for 10 ns;
p1_int_am_i <= "111001"; -- 0x39
p1_int_addr <= X"12345678";
p1_int_vme_go <= '1';
p2_int_vme_go <= '0';
wait for 10 ns;
check_equal(vc1_int_vme_go, '1');
p1_int_vme_go <= '0';
wait for 10 ns;
check_equal(p1_int_vme_go, '0');
elsif run("p1 read with AM=0x19 is directed to core 2") then
wait for 10 ns;
p1_int_am_i <= "011001"; -- 0x19
p1_int_addr <= X"12345678";
p1_int_vme_go <= '1';
p2_int_vme_go <= '0';
wait for 10 ns;
check_equal(vc1_int_vme_go, '0');
check_equal(vc2_int_vme_go, '1');
p1_int_vme_go <= '0';
wait for 10 ns;
check_equal(p1_int_vme_go, '0');
end if;
end loop;
test_runner_cleanup(runner); -- Simulation ends here
end process;
clk <= not clk after 5 ns;
test_runner_watchdog(runner, 250 ns);
dut : entity work.vme_cli_arb
port map (clk => clk,
p1_busy => p1_busy,
p1_int_data_o => p1_int_data_o,
p1_int_data_strobe => p1_int_data_strobe,
p1_int_go_consumed_strobe => p1_int_go_consumed_strobe,
p1_int_blt_decision => p1_int_blt_decision,
p1_int_err_code => p1_int_err_code,
p1_int_addr => p1_int_addr,
p1_int_data_i => p1_int_data_i,
p1_int_am_i => p1_int_am_i,
p1_int_vme_rw => p1_int_vme_rw,
p1_int_vme_go => p1_int_vme_go,
p1_int_blt_decided => p1_int_blt_decided,
p1_int_blt_continue => p1_int_blt_continue,
p1_int_berr_ok => p1_int_berr_ok,
-- Signals to/from the second client.
p2_busy => p2_busy,
p2_int_data_o => p2_int_data_o,
p2_int_data_strobe => p2_int_data_strobe,
p2_int_go_consumed_strobe => p2_int_go_consumed_strobe,
p2_int_blt_decision => p2_int_blt_decision,
p2_int_err_code => p2_int_err_code,
p2_int_addr => p2_int_addr,
p2_int_data_i => p2_int_data_i,
p2_int_am_i => p2_int_am_i,
p2_int_vme_rw => p2_int_vme_rw,
p2_int_vme_go => p2_int_vme_go,
p2_int_blt_decided => p2_int_blt_decided,
p2_int_blt_continue => p2_int_blt_continue,
p2_int_berr_ok => p2_int_berr_ok,
-- Core 1
vc1_busy => vc1_busy,
vc1_int_data_o => vc1_int_data_o,
vc1_int_data_strobe => vc1_int_data_strobe,
vc1_int_go_consumed_strobe => vc1_int_go_consumed_strobe,
vc1_int_blt_decision => vc1_int_blt_decision,
vc1_int_err_code => vc1_int_err_code,
vc1_int_addr => vc1_int_addr,
vc1_int_data_i => vc1_int_data_i,
vc1_int_am_i => vc1_int_am_i,
vc1_int_vme_rw => vc1_int_vme_rw,
vc1_int_vme_go => vc1_int_vme_go,
vc1_int_blt_decided => vc1_int_blt_decided,
vc1_int_blt_continue => vc1_int_blt_continue,
vc1_int_berr_ok => vc1_int_berr_ok,
-- Core 2
vc2_busy => vc2_busy,
vc2_int_data_o => vc2_int_data_o,
vc2_int_data_strobe => vc2_int_data_strobe,
vc2_int_go_consumed_strobe => vc2_int_go_consumed_strobe,
vc2_int_blt_decision => vc2_int_blt_decision,
vc2_int_err_code => vc2_int_err_code,
vc2_int_addr => vc2_int_addr,
vc2_int_data_i => vc2_int_data_i,
vc2_int_am_i => vc2_int_am_i,
vc2_int_vme_rw => vc2_int_vme_rw,
vc2_int_vme_go => vc2_int_vme_go,
vc2_int_blt_decided => vc2_int_blt_decided,
vc2_int_blt_continue => vc2_int_blt_continue,
vc2_int_berr_ok => vc2_int_berr_ok
);
end architecture;
src/vme_data_bus.vhd
View file @ 2fdc70f0
......@@ -730,6 +730,7 @@ begin
-- the address strobe to go high. Instead, it repeatedly
-- drives the data strobe(s) low in response to data transfer
-- acknowledgments from the Slave
last_ds <= vme_ds_n_i;
if (last_ds /= vme_ds_n_i or --
state = IDLE or
......
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