Commit 2c4832bd authored by Michael Munch's avatar Michael Munch
Browse files

Added core arbiter

parent d1978ac0
Pipeline #25543 failed with stage
in 22 seconds
library ieee;
use ieee.std_logic_1164.all;
library vme;
use vme.vme_pkg.all;
-- Multiplex signals between the VME core and two clients.
--
-- Each client sees signals such as if it was the only
-- client connected to the core. (With the exception that it
-- may take a longer time before a 'go' request starts
-- to be processed).
entity vme_core_arb is
generic (
-- To synth formal verification
formal : boolean := true
);
port (
signal clk : in std_logic;
-- Signals to/from the first client.
-- For documentation on the signal purposes, see vme_bus.vhd.
signal cli_busy : out std_logic := '0';
signal cli_int_data_o : out vme_vec_64_t;
signal cli_int_data_strobe : out std_logic := c_DATA_CLEAR;
signal cli_int_go_consumed_strobe : out std_logic := '0';
signal cli_int_blt_decision_strobe : out std_logic := '0';
signal cli_int_err_code : out err_vec_t := C_ERR_OK;
signal cli_int_addr : in vme_addr_t;
signal cli_int_data_i : in vme_vec_64_t;
signal cli_int_am_i : in am_vec_t;
signal cli_int_vme_rw : in std_logic;
signal cli_int_vme_go : in std_logic;
signal cli_int_blt_decided : in std_logic;
signal cli_int_blt_continue : in std_logic;
signal cli_int_berr_ok : in std_logic;
-- Signals to/from the first VME core.
-- Directions inverted relative to the core.
signal vc1_busy : in std_logic := '0';
signal vc1_int_data_o : in vme_vec_64_t;
signal vc1_int_data_strobe : in std_logic := c_DATA_CLEAR;
signal vc1_int_go_consumed_strobe : in std_logic := '0';
signal vc1_int_blt_decision_strobe : in std_logic := '0';
signal vc1_int_err_code : in err_vec_t := C_ERR_OK;
signal vc1_int_addr : out vme_addr_t;
signal vc1_int_data_i : out vme_vec_64_t;
signal vc1_int_am_i : out am_vec_t;
signal vc1_int_vme_rw : out std_logic;
signal vc1_int_vme_go : out std_logic;
signal vc1_int_blt_decided : out std_logic;
signal vc1_int_blt_continue : out std_logic;
signal vc1_int_berr_ok : out std_logic;
-- Signals to/from the second VME core.
-- Directions inverted relative to the core.
signal vc2_busy : in std_logic := '0';
signal vc2_int_data_o : in vme_vec_64_t;
signal vc2_int_data_strobe : in std_logic := c_DATA_CLEAR;
signal vc2_int_go_consumed_strobe : in std_logic := '0';
signal vc2_int_blt_decision_strobe : in std_logic := '0';
signal vc2_int_err_code : in err_vec_t := C_ERR_OK;
signal vc2_int_addr : out vme_addr_t;
signal vc2_int_data_i : out vme_vec_64_t;
signal vc2_int_am_i : out am_vec_t;
signal vc2_int_vme_rw : out std_logic;
signal vc2_int_vme_go : out std_logic;
signal vc2_int_blt_decided : out std_logic;
signal vc2_int_blt_continue : out std_logic;
signal vc2_int_berr_ok : out std_logic
);
end entity;
architecture rtl of vme_core_arb is
signal core_1 : boolean := true;
signal r_busy : std_logic := '0';
signal r_data_o : vme_vec_64_t;
signal r_data_strobe : std_logic := c_DATA_CLEAR;
signal r_go_consumed_strobe : std_logic := '0';
signal r_blt_decision_strobe : std_logic := '0';
signal r_err_code : err_vec_t := C_ERR_OK;
begin
r_busy <= vc1_busy when core_1 else vc2_busy;
r_data_o <= vc1_int_data_o when core_1 else vc2_int_data_o;
r_data_strobe <= vc1_int_data_strobe when core_1 else vc2_int_data_strobe;
r_go_consumed_strobe <= vc1_int_go_consumed_strobe when core_1 else vc2_int_go_consumed_strobe;
r_blt_decision_strobe <= vc1_int_blt_decision_strobe when core_1 else vc2_int_blt_decision_strobe;
r_err_code <= vc1_int_err_code when core_1 else vc2_int_err_code;
vc1_int_addr <= cli_int_addr;
vc1_int_data_i <= cli_int_data_i;
vc1_int_am_i <= cli_int_am_i;
vc1_int_vme_rw <= cli_int_vme_rw;
vc1_int_blt_decided <= cli_int_blt_decided;
vc1_int_blt_continue <= cli_int_blt_continue;
vc1_int_berr_ok <= cli_int_berr_ok;
vc2_int_addr <= cli_int_addr;
vc2_int_data_i <= cli_int_data_i;
vc2_int_am_i <= cli_int_am_i;
vc2_int_vme_rw <= cli_int_vme_rw;
vc2_int_blt_decided <= cli_int_blt_decided;
vc2_int_blt_continue <= cli_int_blt_continue;
vc2_int_berr_ok <= cli_int_berr_ok;
core_1 <= cli_int_am_i /= c_AM_TRLOII;
vc1_int_vme_go <= '1' when cli_int_vme_go = '1' and core_1 else '0';
vc2_int_vme_go <= '1' when cli_int_vme_go = '1' and not core_1 else '0';
end architecture;
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