Commit 2bde4812 authored by Michael Munch's avatar Michael Munch
Browse files

int_vme_rw -> int_vme_write

parent f8a6c067
Pipeline #25924 failed with stage
in 26 seconds
...@@ -76,7 +76,7 @@ architecture tb of tb_vme_bus is ...@@ -76,7 +76,7 @@ architecture tb of tb_vme_bus is
signal int_data_o : std_logic_vector(63 downto 0); signal int_data_o : std_logic_vector(63 downto 0);
signal int_am_i : am_vec_t; signal int_am_i : am_vec_t;
signal int_vme_rw : std_logic; signal int_vme_write : std_logic;
signal int_vme_go : std_logic := '1'; signal int_vme_go : std_logic := '1';
signal int_data_strobe : std_logic; signal int_data_strobe : std_logic;
signal int_blt_decided : std_logic := '0'; signal int_blt_decided : std_logic := '0';
...@@ -156,7 +156,7 @@ begin ...@@ -156,7 +156,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_go <= '1'; int_vme_go <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '1'); int_addr <= (others => '1');
...@@ -179,7 +179,7 @@ begin ...@@ -179,7 +179,7 @@ begin
vme_dtack_n_i <= '0'; vme_dtack_n_i <= '0';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '1'); int_addr <= (others => '1');
...@@ -206,7 +206,7 @@ begin ...@@ -206,7 +206,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_i <= (others => '1');
...@@ -223,7 +223,7 @@ begin ...@@ -223,7 +223,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_i <= (others => '1');
...@@ -258,7 +258,7 @@ begin ...@@ -258,7 +258,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_i <= (others => '1');
...@@ -280,7 +280,7 @@ begin ...@@ -280,7 +280,7 @@ begin
vme_dtack_n_i <= '0'; vme_dtack_n_i <= '0';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_i <= (others => '1');
...@@ -313,7 +313,7 @@ begin ...@@ -313,7 +313,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '1'); int_addr <= (others => '1');
vme_data_i <= (others => '1'); vme_data_i <= (others => '1');
...@@ -342,7 +342,7 @@ begin ...@@ -342,7 +342,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '1'); int_addr <= (others => '1');
vme_data_i <= (others => '1'); vme_data_i <= (others => '1');
...@@ -369,7 +369,7 @@ begin ...@@ -369,7 +369,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '0'); int_addr <= (others => '0');
...@@ -397,7 +397,7 @@ begin ...@@ -397,7 +397,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '0'); int_addr <= (others => '0');
...@@ -416,7 +416,7 @@ begin ...@@ -416,7 +416,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '0'); int_addr <= (others => '0');
...@@ -440,7 +440,7 @@ begin ...@@ -440,7 +440,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_BLT; int_am_i <= c_AM_A24_BLT;
int_addr <= (others => '0'); int_addr <= (others => '0');
...@@ -471,7 +471,7 @@ begin ...@@ -471,7 +471,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_BLT; int_am_i <= c_AM_A24_BLT;
int_addr <= (others => '0'); int_addr <= (others => '0');
...@@ -498,7 +498,7 @@ begin ...@@ -498,7 +498,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_BLT; int_am_i <= c_AM_A24_BLT;
int_addr <= (others => '0'); int_addr <= (others => '0');
...@@ -529,7 +529,7 @@ begin ...@@ -529,7 +529,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_BLT; int_am_i <= c_AM_A24_BLT;
int_addr <= (others => '0'); int_addr <= (others => '0');
...@@ -566,7 +566,7 @@ begin ...@@ -566,7 +566,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_MBLT; int_am_i <= c_AM_A24_MBLT;
int_addr <= (others => '1'); int_addr <= (others => '1');
vme_data_i <= (others => '1'); vme_data_i <= (others => '1');
...@@ -594,7 +594,7 @@ begin ...@@ -594,7 +594,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_MBLT; int_am_i <= c_AM_A24_MBLT;
int_addr <= (others => '1'); int_addr <= (others => '1');
vme_data_i <= (others => '1'); vme_data_i <= (others => '1');
...@@ -623,7 +623,7 @@ begin ...@@ -623,7 +623,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_MBLT; int_am_i <= c_AM_A24_MBLT;
int_addr <= (others => '1'); int_addr <= (others => '1');
vme_data_i <= (others => '1'); vme_data_i <= (others => '1');
...@@ -662,7 +662,7 @@ begin ...@@ -662,7 +662,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_MBLT; int_am_i <= c_AM_A24_MBLT;
int_addr <= (others => '0'); int_addr <= (others => '0');
int_data_i <= (others => '1'); int_data_i <= (others => '1');
...@@ -697,7 +697,7 @@ begin ...@@ -697,7 +697,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_BLT; int_am_i <= c_AM_A24_BLT;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_i <= (others => '1');
...@@ -715,7 +715,7 @@ begin ...@@ -715,7 +715,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_BLT; int_am_i <= c_AM_A24_BLT;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_i <= (others => '1');
...@@ -742,7 +742,7 @@ begin ...@@ -742,7 +742,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_BLT; int_am_i <= c_AM_A24_BLT;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_i <= (others => '1');
...@@ -777,7 +777,7 @@ begin ...@@ -777,7 +777,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_WRITE; int_vme_write <= c_VME_WRITE;
int_am_i <= c_AM_A24_BLT; int_am_i <= c_AM_A24_BLT;
int_addr <= (others => '1'); int_addr <= (others => '1');
int_data_i <= (others => '1'); int_data_i <= (others => '1');
...@@ -819,7 +819,7 @@ begin ...@@ -819,7 +819,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '0'); int_addr <= (others => '0');
...@@ -847,7 +847,7 @@ begin ...@@ -847,7 +847,7 @@ begin
vme_dtack_n_i <= '1'; vme_dtack_n_i <= '1';
vme_berr_n_i <= '1'; vme_berr_n_i <= '1';
int_vme_rw <= c_VME_READ; int_vme_write <= c_VME_READ;
int_am_i <= c_AM_A24_DATA; int_am_i <= c_AM_A24_DATA;
int_addr <= (others => '0'); int_addr <= (others => '0');
...@@ -958,7 +958,7 @@ begin ...@@ -958,7 +958,7 @@ begin
int_data_i => int_data_i, int_data_i => int_data_i,
int_data_o => int_data_o, int_data_o => int_data_o,
int_am_i => int_am_i, int_am_i => int_am_i,
int_vme_rw => int_vme_rw, int_vme_write => int_vme_write,
int_vme_go => int_vme_go, int_vme_go => int_vme_go,
int_err_code => int_err_code, int_err_code => int_err_code,
int_data_strobe => int_data_strobe, int_data_strobe => int_data_strobe,
......
...@@ -32,7 +32,7 @@ entity vme_cli_arb is ...@@ -32,7 +32,7 @@ entity vme_cli_arb is
signal p1_int_addr : in vme_addr_t; signal p1_int_addr : in vme_addr_t;
signal p1_int_data_i : in vme_vec_64_t; signal p1_int_data_i : in vme_vec_64_t;
signal p1_int_am_i : in am_vec_t; signal p1_int_am_i : in am_vec_t;
signal p1_int_vme_rw : in std_logic; signal p1_int_vme_write : in std_logic;
signal p1_int_vme_go : in std_logic; signal p1_int_vme_go : in std_logic;
signal p1_int_blt_decided : in std_logic; signal p1_int_blt_decided : in std_logic;
...@@ -53,7 +53,7 @@ entity vme_cli_arb is ...@@ -53,7 +53,7 @@ entity vme_cli_arb is
signal p2_int_addr : in vme_addr_t; signal p2_int_addr : in vme_addr_t;
signal p2_int_data_i : in vme_vec_64_t; signal p2_int_data_i : in vme_vec_64_t;
signal p2_int_am_i : in am_vec_t; signal p2_int_am_i : in am_vec_t;
signal p2_int_vme_rw : in std_logic; signal p2_int_vme_write : in std_logic;
signal p2_int_vme_go : in std_logic; signal p2_int_vme_go : in std_logic;
signal p2_int_blt_decided : in std_logic; signal p2_int_blt_decided : in std_logic;
...@@ -75,7 +75,7 @@ entity vme_cli_arb is ...@@ -75,7 +75,7 @@ entity vme_cli_arb is
signal vc_int_addr : out vme_addr_t; signal vc_int_addr : out vme_addr_t;
signal vc_int_data_i : out vme_vec_64_t; signal vc_int_data_i : out vme_vec_64_t;
signal vc_int_am_i : out am_vec_t; signal vc_int_am_i : out am_vec_t;
signal vc_int_vme_rw : out std_logic; signal vc_int_vme_write : out std_logic;
signal vc_int_vme_go : out std_logic; signal vc_int_vme_go : out std_logic;
signal vc_int_blt_decided : out std_logic; signal vc_int_blt_decided : out std_logic;
...@@ -201,7 +201,7 @@ begin ...@@ -201,7 +201,7 @@ begin
vc_int_addr <= p1_int_addr when live_1 else p2_int_addr; vc_int_addr <= p1_int_addr when live_1 else p2_int_addr;
vc_int_data_i <= p1_int_data_i when live_1 else p2_int_data_i; vc_int_data_i <= p1_int_data_i when live_1 else p2_int_data_i;
vc_int_am_i <= p1_int_am_i when live_1 else p2_int_am_i; vc_int_am_i <= p1_int_am_i when live_1 else p2_int_am_i;
vc_int_vme_rw <= p1_int_vme_rw when live_1 else p2_int_vme_rw; vc_int_vme_write <= p1_int_vme_write when live_1 else p2_int_vme_write;
vc_int_vme_go <= p1_int_vme_go when live_1 else p2_int_vme_go; vc_int_vme_go <= p1_int_vme_go when live_1 else p2_int_vme_go;
vc_int_blt_decided <= p1_int_blt_decided when live_1 else p2_int_blt_decided; vc_int_blt_decided <= p1_int_blt_decided when live_1 else p2_int_blt_decided;
vc_int_blt_continue <= p1_int_blt_continue when live_1 else p2_int_blt_continue; vc_int_blt_continue <= p1_int_blt_continue when live_1 else p2_int_blt_continue;
...@@ -308,7 +308,7 @@ begin ...@@ -308,7 +308,7 @@ begin
-- psl p1_vme_am_i: assert always {p1_int_vme_go} -- psl p1_vme_am_i: assert always {p1_int_vme_go}
-- |=> eventually! vc_int_am_i = p1_int_am_i ; -- |=> eventually! vc_int_am_i = p1_int_am_i ;
-- psl p1_vme_rw: assert always {p1_int_vme_go} -- psl p1_vme_rw: assert always {p1_int_vme_go}
-- |=> eventually! vc_int_vme_rw = p1_int_vme_rw ; -- |=> eventually! vc_int_vme_write = p1_int_vme_write ;
-- psl p1_vme_go: assert always {p1_int_vme_go} -- psl p1_vme_go: assert always {p1_int_vme_go}
-- |=> eventually! vc_int_vme_go = p1_int_vme_go ; -- |=> eventually! vc_int_vme_go = p1_int_vme_go ;
-- psl p1_vme_blt_deci: assert always {p1_int_vme_go} -- psl p1_vme_blt_deci: assert always {p1_int_vme_go}
...@@ -326,7 +326,7 @@ begin ...@@ -326,7 +326,7 @@ begin
-- psl p2_vme_am_i: assert always {p2_int_vme_go} -- psl p2_vme_am_i: assert always {p2_int_vme_go}
-- |=> eventually! vc_int_am_i = p2_int_am_i ; -- |=> eventually! vc_int_am_i = p2_int_am_i ;
-- psl p2_vme_rw: assert always {p2_int_vme_go} -- psl p2_vme_rw: assert always {p2_int_vme_go}
-- |=> eventually! vc_int_vme_rw = p2_int_vme_rw ; -- |=> eventually! vc_int_vme_write = p2_int_vme_write ;
-- psl p2_vme_go: assert always {p2_int_vme_go} -- psl p2_vme_go: assert always {p2_int_vme_go}
-- |=> eventually! vc_int_vme_go = p2_int_vme_go ; -- |=> eventually! vc_int_vme_go = p2_int_vme_go ;
-- psl p2_vme_blt_deci: assert always {p2_int_vme_go} -- psl p2_vme_blt_deci: assert always {p2_int_vme_go}
......
...@@ -38,7 +38,7 @@ entity vme_core_arb is ...@@ -38,7 +38,7 @@ entity vme_core_arb is
signal cli_int_addr : in vme_addr_t; signal cli_int_addr : in vme_addr_t;
signal cli_int_data_i : in vme_vec_64_t; signal cli_int_data_i : in vme_vec_64_t;
signal cli_int_am_i : in am_vec_t; signal cli_int_am_i : in am_vec_t;
signal cli_int_vme_rw : in std_logic; signal cli_int_vme_write : in std_logic;
signal cli_int_vme_go : in std_logic; signal cli_int_vme_go : in std_logic;
signal cli_int_blt_decided : in std_logic; signal cli_int_blt_decided : in std_logic;
...@@ -59,7 +59,7 @@ entity vme_core_arb is ...@@ -59,7 +59,7 @@ entity vme_core_arb is
signal vc1_int_addr : out vme_addr_t; signal vc1_int_addr : out vme_addr_t;
signal vc1_int_data_i : out vme_vec_64_t; signal vc1_int_data_i : out vme_vec_64_t;
signal vc1_int_am_i : out am_vec_t; signal vc1_int_am_i : out am_vec_t;
signal vc1_int_vme_rw : out std_logic; signal vc1_int_vme_write : out std_logic;
signal vc1_int_vme_go : out std_logic; signal vc1_int_vme_go : out std_logic;
signal vc1_int_blt_decided : out std_logic; signal vc1_int_blt_decided : out std_logic;
...@@ -80,7 +80,7 @@ entity vme_core_arb is ...@@ -80,7 +80,7 @@ entity vme_core_arb is
signal vc2_int_addr : out vme_addr_t; signal vc2_int_addr : out vme_addr_t;
signal vc2_int_data_i : out vme_vec_64_t; signal vc2_int_data_i : out vme_vec_64_t;
signal vc2_int_am_i : out am_vec_t; signal vc2_int_am_i : out am_vec_t;
signal vc2_int_vme_rw : out std_logic; signal vc2_int_vme_write : out std_logic;
signal vc2_int_vme_go : out std_logic; signal vc2_int_vme_go : out std_logic;
signal vc2_int_blt_decided : out std_logic; signal vc2_int_blt_decided : out std_logic;
...@@ -109,7 +109,7 @@ begin ...@@ -109,7 +109,7 @@ begin
vc1_int_addr <= cli_int_addr; vc1_int_addr <= cli_int_addr;
vc1_int_data_i <= cli_int_data_i; vc1_int_data_i <= cli_int_data_i;
vc1_int_am_i <= cli_int_am_i; vc1_int_am_i <= cli_int_am_i;
vc1_int_vme_rw <= cli_int_vme_rw; vc1_int_vme_write <= cli_int_vme_write;
vc1_int_blt_decided <= cli_int_blt_decided; vc1_int_blt_decided <= cli_int_blt_decided;
vc1_int_blt_continue <= cli_int_blt_continue; vc1_int_blt_continue <= cli_int_blt_continue;
vc1_int_berr_ok <= cli_int_berr_ok; vc1_int_berr_ok <= cli_int_berr_ok;
...@@ -117,7 +117,7 @@ begin ...@@ -117,7 +117,7 @@ begin
vc2_int_addr <= cli_int_addr; vc2_int_addr <= cli_int_addr;
vc2_int_data_i <= cli_int_data_i; vc2_int_data_i <= cli_int_data_i;
vc2_int_am_i <= cli_int_am_i; vc2_int_am_i <= cli_int_am_i;
vc2_int_vme_rw <= cli_int_vme_rw; vc2_int_vme_write <= cli_int_vme_write;
vc2_int_blt_decided <= cli_int_blt_decided; vc2_int_blt_decided <= cli_int_blt_decided;
vc2_int_blt_continue <= cli_int_blt_continue; vc2_int_blt_continue <= cli_int_blt_continue;
vc2_int_berr_ok <= cli_int_berr_ok; vc2_int_berr_ok <= cli_int_berr_ok;
......
...@@ -176,7 +176,7 @@ entity vme_data_bus is ...@@ -176,7 +176,7 @@ entity vme_data_bus is
signal int_am_i : in am_vec_t; signal int_am_i : in am_vec_t;
-- signal int_vme_op : in VME_OP; -- signal int_vme_op : in VME_OP;
signal int_vme_rw : in std_logic; signal int_vme_write : in std_logic;
signal int_vme_go : in std_logic; signal int_vme_go : in std_logic;
...@@ -348,7 +348,7 @@ begin ...@@ -348,7 +348,7 @@ begin
l_addr <= int_addr; l_addr <= int_addr;
l_data <= int_data_i; l_data <= int_data_i;
l_am <= int_am_i; l_am <= int_am_i;
l_rw <= int_vme_rw; l_rw <= int_vme_write;
l_transfer_mode <= transfer_mode; l_transfer_mode <= transfer_mode;
l_addr_mode <= addr_mode; l_addr_mode <= addr_mode;
busy <= '1'; busy <= '1';
...@@ -361,7 +361,7 @@ begin ...@@ -361,7 +361,7 @@ begin
vme_am_o <= int_am_i; vme_am_o <= int_am_i;
vme_am_dir <= c_PIN_OUT; vme_am_dir <= c_PIN_OUT;
vme_write_n_o <= not int_vme_rw; vme_write_n_o <= not int_vme_write;
vme_iack_n_o <= '1'; -- We pull IACK* high vme_iack_n_o <= '1'; -- We pull IACK* high
...@@ -370,7 +370,7 @@ begin ...@@ -370,7 +370,7 @@ begin
-- If data lines are free then place data on them -- If data lines are free then place data on them
-- We also do this in MBLT mode. -- We also do this in MBLT mode.
if (--transfer_mode /= MBLT and if (--transfer_mode /= MBLT and
int_vme_rw = c_VME_WRITE and int_vme_write = c_VME_WRITE and
vme_dtack_n_i = '1') vme_dtack_n_i = '1')
then then
vme_data_o <= int_data_i(31 downto 0); vme_data_o <= int_data_i(31 downto 0);
...@@ -773,7 +773,7 @@ begin ...@@ -773,7 +773,7 @@ begin
if (state = IDLE and int_vme_go = '1') then if (state = IDLE and int_vme_go = '1') then
f_addr <= int_addr; f_addr <= int_addr;
f_am <= int_am_i; f_am <= int_am_i;
f_vme_rw <= int_vme_rw; f_vme_rw <= int_vme_write;
f_data <= int_data_i; f_data <= int_data_i;
end if; end if;
...@@ -904,7 +904,7 @@ begin ...@@ -904,7 +904,7 @@ begin
-- -- Then place low 32 bits immideately -- -- Then place low 32 bits immideately
-- psl when_writing_and_dtack_is_high_then_data_is_placed: -- psl when_writing_and_dtack_is_high_then_data_is_placed:
-- assert always {int_vme_go = '1' and state = IDLE -- assert always {int_vme_go = '1' and state = IDLE
-- and int_vme_rw = c_VME_WRITE and vme_dtack_n_i = '1' -- and int_vme_write = c_VME_WRITE and vme_dtack_n_i = '1'
-- and int_am_i = c_AM_A24_DATA} -- and int_am_i = c_AM_A24_DATA}
-- |=> vme_data_o = l_data(31 downto 0) -- |=> vme_data_o = l_data(31 downto 0)
-- until state = DTACK_LOW_WAIT or state = IDLE; -- until state = DTACK_LOW_WAIT or state = IDLE;
......
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