Commit 27de41b9 authored by Michael Munch's avatar Michael Munch
Browse files

Added blt_decided_consumed

parent ed97919d
Pipeline #33661 passed with stage
in 34 seconds
...@@ -27,6 +27,7 @@ entity vme_cli_arb is ...@@ -27,6 +27,7 @@ entity vme_cli_arb is
signal p1_int_data_strobe : out std_logic := c_DATA_CLEAR; signal p1_int_data_strobe : out std_logic := c_DATA_CLEAR;
signal p1_int_go_consumed_strobe : out std_logic := '0'; signal p1_int_go_consumed_strobe : out std_logic := '0';
signal p1_int_blt_decision : out std_logic := '0'; signal p1_int_blt_decision : out std_logic := '0';
signal p1_int_blt_decided_consumed : out std_logic := '0';
signal p1_int_err_code : out err_vec_t := C_ERR_OK; signal p1_int_err_code : out err_vec_t := C_ERR_OK;
signal p1_int_addr : in vme_addr_t; signal p1_int_addr : in vme_addr_t;
...@@ -48,6 +49,7 @@ entity vme_cli_arb is ...@@ -48,6 +49,7 @@ entity vme_cli_arb is
signal p2_int_data_strobe : out std_logic := c_DATA_CLEAR; signal p2_int_data_strobe : out std_logic := c_DATA_CLEAR;
signal p2_int_go_consumed_strobe : out std_logic := '0'; signal p2_int_go_consumed_strobe : out std_logic := '0';
signal p2_int_blt_decision : out std_logic := '0'; signal p2_int_blt_decision : out std_logic := '0';
signal p2_int_blt_decided_consumed : out std_logic := '0';
signal p2_int_err_code : out err_vec_t := C_ERR_OK; signal p2_int_err_code : out err_vec_t := C_ERR_OK;
signal p2_int_addr : in vme_addr_t; signal p2_int_addr : in vme_addr_t;
...@@ -70,6 +72,7 @@ entity vme_cli_arb is ...@@ -70,6 +72,7 @@ entity vme_cli_arb is
signal vc_int_data_strobe : in std_logic := c_DATA_CLEAR; signal vc_int_data_strobe : in std_logic := c_DATA_CLEAR;
signal vc_int_go_consumed_strobe : in std_logic := '0'; signal vc_int_go_consumed_strobe : in std_logic := '0';
signal vc_int_blt_decision : in std_logic := '0'; signal vc_int_blt_decision : in std_logic := '0';
signal vc_int_blt_decided_consumed : in std_logic := '0';
signal vc_int_err_code : in err_vec_t := C_ERR_OK; signal vc_int_err_code : in err_vec_t := C_ERR_OK;
signal vc_int_addr : out vme_addr_t; signal vc_int_addr : out vme_addr_t;
...@@ -230,6 +233,9 @@ begin ...@@ -230,6 +233,9 @@ begin
p1_int_blt_decision <= vc_int_blt_decision when live_1 else '0'; p1_int_blt_decision <= vc_int_blt_decision when live_1 else '0';
p2_int_blt_decision <= vc_int_blt_decision when live_2 else '0'; p2_int_blt_decision <= vc_int_blt_decision when live_2 else '0';
p1_int_blt_decided_consumed <= vc_int_blt_decided_consumed when live_1 else '0';
p2_int_blt_decided_consumed <= vc_int_blt_decided_consumed when live_2 else '0';
-- The busy of a client is simply while it is live. -- The busy of a client is simply while it is live.
-- This actually means that we will report busy some cycles -- This actually means that we will report busy some cycles
-- early. (But the clients are not likely to use this signal...) -- early. (But the clients are not likely to use this signal...)
......
...@@ -33,6 +33,7 @@ entity vme_core_arb is ...@@ -33,6 +33,7 @@ entity vme_core_arb is
signal cli_int_data_strobe : out std_logic := c_DATA_CLEAR; signal cli_int_data_strobe : out std_logic := c_DATA_CLEAR;
signal cli_int_go_consumed_strobe : out std_logic := '0'; signal cli_int_go_consumed_strobe : out std_logic := '0';
signal cli_int_blt_decision : out std_logic := '0'; signal cli_int_blt_decision : out std_logic := '0';
signal cli_int_blt_decided_consumed : out std_logic := '0';
signal cli_int_err_code : out err_vec_t := C_ERR_OK; signal cli_int_err_code : out err_vec_t := C_ERR_OK;
signal cli_int_addr : in vme_addr_t; signal cli_int_addr : in vme_addr_t;
...@@ -54,6 +55,7 @@ entity vme_core_arb is ...@@ -54,6 +55,7 @@ entity vme_core_arb is
signal vc1_int_data_strobe : in std_logic := c_DATA_CLEAR; signal vc1_int_data_strobe : in std_logic := c_DATA_CLEAR;
signal vc1_int_go_consumed_strobe : in std_logic := '0'; signal vc1_int_go_consumed_strobe : in std_logic := '0';
signal vc1_int_blt_decision : in std_logic := '0'; signal vc1_int_blt_decision : in std_logic := '0';
signal vc1_int_blt_decided_consumed : in std_logic := '0';
signal vc1_int_err_code : in err_vec_t := C_ERR_OK; signal vc1_int_err_code : in err_vec_t := C_ERR_OK;
signal vc1_int_addr : out vme_addr_t; signal vc1_int_addr : out vme_addr_t;
...@@ -75,6 +77,7 @@ entity vme_core_arb is ...@@ -75,6 +77,7 @@ entity vme_core_arb is
signal vc2_int_data_strobe : in std_logic := c_DATA_CLEAR; signal vc2_int_data_strobe : in std_logic := c_DATA_CLEAR;
signal vc2_int_go_consumed_strobe : in std_logic := '0'; signal vc2_int_go_consumed_strobe : in std_logic := '0';
signal vc2_int_blt_decision : in std_logic := '0'; signal vc2_int_blt_decision : in std_logic := '0';
signal vc2_int_blt_decided_consumed : in std_logic := '0';
signal vc2_int_err_code : in err_vec_t := C_ERR_OK; signal vc2_int_err_code : in err_vec_t := C_ERR_OK;
signal vc2_int_addr : out vme_addr_t; signal vc2_int_addr : out vme_addr_t;
...@@ -98,10 +101,11 @@ architecture rtl of vme_core_arb is ...@@ -98,10 +101,11 @@ architecture rtl of vme_core_arb is
begin begin
-- cli_busy <= '1' when vc1_busy = '1' or vc2_busy = '1' else '0'; -- cli_busy <= '1' when vc1_busy = '1' or vc2_busy = '1' else '0';
cli_busy <= vc1_busy or vc2_busy; cli_busy <= vc1_busy or vc2_busy;
cli_int_data_strobe <= vc1_int_data_strobe or vc2_int_data_strobe; cli_int_data_strobe <= vc1_int_data_strobe or vc2_int_data_strobe;
cli_int_blt_decision <= vc1_int_blt_decision or vc2_int_blt_decision; cli_int_blt_decision <= vc1_int_blt_decision or vc2_int_blt_decision;
cli_int_go_consumed_strobe <= vc1_int_go_consumed_strobe or vc2_int_go_consumed_strobe; cli_int_blt_decided_consumed <= vc1_int_blt_decided_consumed or vc2_int_blt_decided_consumed;
cli_int_go_consumed_strobe <= vc1_int_go_consumed_strobe or vc2_int_go_consumed_strobe;
cli_int_data_read <= vc1_int_data_read when core_1 else vc2_int_data_read; cli_int_data_read <= vc1_int_data_read when core_1 else vc2_int_data_read;
cli_int_err_code <= vc1_int_err_code when core_1 else vc2_int_err_code; cli_int_err_code <= vc1_int_err_code when core_1 else vc2_int_err_code;
......
...@@ -166,6 +166,10 @@ entity vme_data_bus is ...@@ -166,6 +166,10 @@ entity vme_data_bus is
-- See int_blt_decided and int_blt_continue -- See int_blt_decided and int_blt_continue
signal int_blt_decision : out std_logic := '0'; signal int_blt_decision : out std_logic := '0';
-- Strobe that indicates that the BLT decision has
-- been consumed.
signal int_blt_decided_consumed : out std_logic := '0';
-- Error code. -- Error code.
-- Consult vme_pkg.ERR_CODE for valid values. -- Consult vme_pkg.ERR_CODE for valid values.
-- Will be vme_pkg.ERR_CODE.OK if no problems. -- Will be vme_pkg.ERR_CODE.OK if no problems.
...@@ -295,6 +299,7 @@ begin ...@@ -295,6 +299,7 @@ begin
-- Strobes are by default '0', and only set when fired -- Strobes are by default '0', and only set when fired
int_data_strobe <= c_DATA_CLEAR; int_data_strobe <= c_DATA_CLEAR;
int_go_consumed_strobe <= '0'; int_go_consumed_strobe <= '0';
int_blt_decided_consumed <= '0';
-- Common delay counter -- Common delay counter
if (n_wait /= 0) then if (n_wait /= 0) then
...@@ -623,6 +628,7 @@ begin ...@@ -623,6 +628,7 @@ begin
when BLT_WRITE_WAIT => when BLT_WRITE_WAIT =>
if int_blt_decided = '1' then if int_blt_decided = '1' then
int_blt_decision <= '0'; int_blt_decision <= '0';
int_blt_decided_consumed <= '1';
if int_blt_continue = '1' then if int_blt_continue = '1' then
l_data <= int_data_write; -- Latch new data l_data <= int_data_write; -- Latch new data
...@@ -639,6 +645,7 @@ begin ...@@ -639,6 +645,7 @@ begin
when BLT_READ_WAIT => when BLT_READ_WAIT =>
if int_blt_decided = '1' then if int_blt_decided = '1' then
int_blt_decision <= '0'; int_blt_decision <= '0';
int_blt_decided_consumed <= '1';
if int_blt_continue = '1' then if int_blt_continue = '1' then
state <= DTACK_HIGH_WAIT; state <= DTACK_HIGH_WAIT;
else else
......
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