Commit 1e3a72ff authored by Michael Munch's avatar Michael Munch
Browse files

Things compile

parent 7dd2a905
Pipeline #13926 passed with stage
in 37 seconds
......@@ -35,6 +35,8 @@ entity vme_cli_arb is
signal p1_int_berr_ok : in std_logic;
signal p1_go : in std_logic;
-- Signals to/from the second client.
signal p2_busy : out std_logic := '0';
......@@ -56,6 +58,8 @@ entity vme_cli_arb is
signal p2_int_berr_ok : in std_logic;
signal p2_go : in std_logic;
-- Signals to/from the VME core.
-- Directions inverted relative to the core.
......@@ -99,9 +103,9 @@ end entity;
architecture rtl of vme_cli_arb is
signal state : vme_data_state := STOPPED;
signal addr_mode : addr_type_t;
signal transfer_mode : transfer_type_t;
-- signal state : vme_data_state := STOPPED;
-- signal addr_mode : addr_type_t;
-- signal transfer_mode : transfer_type_t;
......@@ -124,26 +128,31 @@ architecture rtl of vme_cli_arb is
-- Who will we prefer when we can take the next client, i.e. are
-- no longer busy?
signal prefer_1 : std_logic := '1';
signal prefer_1 : boolean := false;
signal p1_int_data_o_latched : vme_vec_64_t;
signal p2_int_data_o_latched : vme_vec_64_t;
signal p1_int_err_code_latched : ERR_CODE := OK;
signal p2_int_err_code_latched : ERR_CODE := OK;
begin
want_1 <= (go_1 and not go_2) or (go_1 and prefer_1);
want_2 <= (go_2 and not go_1) or (go_2 and not prefer_1);
want_1 <= (p1_go = '1' and p2_go = '0') or (p1_go = '1' and prefer_1);
want_2 <= (p2_go = '1' and p1_go = '0') or (p2_go = '1' and not prefer_1);
start_1 <= not busy and want_1;
start_2 <= not busy and want_2;
start_1 <= vc_busy = '0' and want_1;
start_2 <= vc_busy = '0' and want_2;
-- We kill the live assignment as soon as busy is removed.
-- (Not really needed.)
live_1 <= (active_1 and busy) or start_1;
live_2 <= (active_2 and busy) or start_2;
live_1 <= (active_1 and vc_busy = '1') or start_1;
live_2 <= (active_2 and vc_busy = '1') or start_2;
process (clk)
begin
if (rising_edge(clk)) then
if (not busy) then
if (vc_busy = '0') then
active_1 <= false;
active_2 <= false;
end if;
......@@ -161,11 +170,11 @@ begin
-- We select on active instead of live, since active is cheaper (comes
-- directly from a flip-flop, instead of logic), and
-- vc_int_data_strobe will not come on the first cycle.
if (active_1 and vc_int_data_strobe) then
if (active_1 and vc_int_data_strobe = '1') then
p1_int_data_o_latched <= vc_int_data_o;
p1_int_err_code_latched <= vc_int_err_code;
end if;
if (active_2 and vc_int_data_strobe) then
if (active_2 and vc_int_data_strobe = '1') then
p2_int_data_o_latched <= vc_int_data_o;
p2_int_err_code_latched <= vc_int_err_code;
end if;
......@@ -180,14 +189,14 @@ begin
-- client 2. This does not matter, since the VME core will
-- only react to anything if the 'go' signal is given.
vc_int_addr <= p1_int_addr when live_1 else p2_int_addr;
vc_int_data_i <= p1_int_data_i when live_1 else p2_int_data_i;
vc_int_am_i <= p1_int_am_i when live_1 else p2_int_am_i;
vc_int_vme_rw <= p1_int_vme_rw when live_1 else p2_int_vme_rw;
vc_int_vme_go <= p1_int_vme_go when live_1 else p2_int_vme_go;
vc_int_blt_decided <= p1_int_blt_decided when live_1 else p2_int_blt_decided;
vc_int_blt_cont <= p1_int_blt_cont when live_1 else p2_int_blt_cont;
vc_int_berr_ok <= p1_int_berr_ok when live_1 else p2_int_berr_ok;
vc_int_addr <= p1_int_addr when live_1 else p2_int_addr;
vc_int_data_i <= p1_int_data_i when live_1 else p2_int_data_i;
vc_int_am_i <= p1_int_am_i when live_1 else p2_int_am_i;
vc_int_vme_rw <= p1_int_vme_rw when live_1 else p2_int_vme_rw;
vc_int_vme_go <= p1_int_vme_go when live_1 else p2_int_vme_go;
vc_int_blt_decided <= p1_int_blt_decided when live_1 else p2_int_blt_decided;
vc_int_blt_continue <= p1_int_blt_continue when live_1 else p2_int_blt_continue;
vc_int_berr_ok <= p1_int_berr_ok when live_1 else p2_int_berr_ok;
-- Signals to the clients from the VME core:
......@@ -197,14 +206,14 @@ begin
-- Data is passed directly through on the cycle they have been latched.
-- Otherwise, take the latched value:
p1_int_data_o <= vc_int_data_o when (live_1 and vc_int_data_strobe) else
p1_int_data_o <= vc_int_data_o when (live_1 and vc_int_data_strobe = '1') else
p1_int_data_o_latched;
p2_int_data_o <= vc_int_data_o when (live_2 and vc_int_data_strobe) else
p2_int_data_o <= vc_int_data_o when (live_2 and vc_int_data_strobe = '1') else
p2_int_data_o_latched;
-- The error code follows the data.
p1_int_err_code <= vc_int_err_code when (live_1 and vc_int_data_strobe) else
p1_int_err_code <= vc_int_err_code when (live_1 and vc_int_data_strobe = '1') else
p1_int_err_code_latched;
p2_int_err_code <= vc_int_err_code when (live_2 and vc_int_data_strobe) else
p2_int_err_code <= vc_int_err_code when (live_2 and vc_int_data_strobe = '1') else
p2_int_err_code_latched;
-- The strobes always go to the live client.
......@@ -220,8 +229,8 @@ begin
-- The busy of a client is simply while it is live.
-- This actually means that we will report busy some cycles
-- early. (But the clients are not likely to use this signal...)
p1_busy <= live_1;
p2_busy <= live_2;
p1_busy <= '1' when live_1 else '0';
p2_busy <= '1' when live_2 else '0';
end architecture;
......
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