Commit 1565f5fc authored by Michael Munch's avatar Michael Munch
Browse files

Possible to select on magic address

parent a83b3fea
Pipeline #25557 failed with stage
in 15 seconds
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vme;
use vme.vme_pkg.all;
-- Multiplex signals between the VME core and two clients.
-- Multiplex signals between a client and two cores.
--
-- All signals from the client, except go, is forwarded
-- to both core. The go signals is only forwarded to the
-- selected core.
--
-- Each client sees signals such as if it was the only
-- client connected to the core. (With the exception that it
-- may take a longer time before a 'go' request starts
-- to be processed).
-- All requests are directed to core 1 unless a special AM
-- code or magic address is used.
entity vme_core_arb is
generic (
-- To synth formal verification
formal : boolean := true
am_select : boolean := false;
am_magic : am_vec_t := c_AM_TRLOII;
addr_select : boolean := true;
addr_magic : natural range 0 to 255 := 255
);
port (
signal clk : in std_logic;
......@@ -88,6 +94,7 @@ end entity;
architecture rtl of vme_core_arb is
signal core_1 : boolean := true;
signal addr_magic_slv : std_logic_vector(cli_int_addr'high downto cli_int_addr'high - 8 + 1);
begin
-- cli_busy <= '1' when vc1_busy = '1' or vc2_busy = '1' else '0';
......@@ -116,7 +123,17 @@ begin
vc2_int_berr_ok <= cli_int_berr_ok;
core_1 <= cli_int_am_i /= c_AM_TRLOII;
G_AM_SELECT : if am_select generate
core_1 <= cli_int_am_i /= am_magic;
end generate;
G_ADDR_SELECT : if addr_select generate
addr_magic_slv <= std_logic_vector(to_unsigned(addr_magic, addr_magic_slv'length));
core_1 <= addr_magic_slv /=
cli_int_addr(addr_magic_slv'high downto addr_magic_slv'low);
end generate;
vc1_int_vme_go <= '1' when cli_int_vme_go = '1' and core_1 else '0';
vc2_int_vme_go <= '1' when cli_int_vme_go = '1' and not core_1 else '0';
end architecture;
......
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