vme_data_bus.vhd 34.5 KB
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library ieee;
use ieee.std_logic_1164.all;
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library vme;
use vme.vme_pkg.all;
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entity vme_data_bus is
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  generic (
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    CLOCK_PERIOD  : integer := 10;
    FORMAL        : boolean := true
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    );
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  port (
    signal clk      : in std_logic; -- CLOCK with period CLOCK_PERIOD
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    -- _n indicate active low (inverted) signals
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    signal vme_addr_i		: in std_logic_vector(31 downto 0);
    signal vme_addr_o		: out std_logic_vector(31 downto 0);
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    signal vme_addr_dir		: out std_logic := c_PIN_IN;
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    signal vme_addr_oe_n	: out std_logic := c_OE_OFF;
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    signal vme_am_i		: in am_vec_t;
    signal vme_am_o		: out am_vec_t;
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    signal vme_am_dir		: out std_logic := c_PIN_IN;
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--    signal vme_am_oe_n	: out std_logic -- Shared with addr
    signal vme_write_n_i        : in std_logic;
    signal vme_write_n_o        : out std_logic;
    -- write shares DIR and OE with AM
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    signal vme_data_i		: in std_logic_vector(31 downto 0);
    signal vme_data_o		: out std_logic_vector(31 downto 0);
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    signal vme_data_dir		: out std_logic := c_PIN_IN;
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    signal vme_data_oe_n	: out std_logic := c_OE_OFF;
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    signal vme_as_n_i		: in std_logic;
    signal vme_as_n_o		: out std_logic;
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    signal vme_as_n_dir		: out std_logic := c_PIN_IN;
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    signal vme_iack_n_i		: in std_logic;
    signal vme_iack_n_o		: out std_logic;
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    signal vme_iack_n_dir	: out std_logic := c_PIN_IN;
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    -- Always enabled, always input
    signal vme_iackin_n		: in std_logic;

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    -- Enable IACKOUT_n. Will be pulled low
    signal vme_iackout_n_oe_n	: out std_logic := c_OE_OFF;
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    signal vme_dtack_n_i	: in std_logic;
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--    signal vme_dtack_n_o	: out std_logic;
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    signal vme_dtack_n_dir	: out std_logic := c_PIN_IN;
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--    signal vme_retry_i	        : in std_logic;
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--    signal vme_retry_o	        : out std_logic;
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--    signal vme_retry_dir	: out std_logic := c_PIN_IN;
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    signal vme_ds_n_i	        : in std_logic_vector(1 downto 0);
    signal vme_ds_n_o	        : out std_logic_vector(1 downto 0);
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    signal vme_ds_n_dir	        : out std_logic := c_PIN_IN;
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    signal vme_berr_n_i         : in std_logic;
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    signal vme_berr_n_o         : out std_logic;
    signal vme_berr_n_dir       : out std_logic;
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    ---------------------------------
    -- SYS CONTROL START           --
    ---------------------------------

    -- signal vme_sysreset_n_i     : in std_logic;
    -- signal vme_sysreset_n_o     : out std_logic;
    -- signal vme_sysreset_n_dir   : out std_logic

    -- signal vme_sysfail_n_i     : in std_logic;
    -- signal vme_sysfail_n_o     : out std_logic;
    -- signal vme_sysfail_n_dir   : out std_logic

    -- signal vme_sysclk_i     : in std_logic;
    -- signal vme_sysclk_o     : out std_logic;
    -- signal vme_sysclk_dir   : out std_logic

    ---------------------------------
    -- SYS CONTROL END             --
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    ---------------------------------
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    ---------------------------------
    -- BUS REQUEST START           --
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    ---------------------------------
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    -- signal vme_br_n_i		: in std_logic_vector(3 downto 0);
    -- signal vme_br_n_o		: out std_logic_vector(3 downto 0);
    -- signal vme_br_n_dir		: out std_logic;
    -- signal vme_br_n_oe_n	: out std_logic;
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    -- -- Fixed DIR = input
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    -- signal vme_bgin_n_i		: in std_logic_vector(3 downto 0);
    -- signal vme_bgin_n_oe_n	: out std_logic;
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    -- -- Fixed DIR = output
    -- signal vme_bgout_n_o	: out std_logic_vector(3 downto 0);
    -- signal vme_bgout_n_oe_n	: out std_logic;
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    -- signal vme_bbsy_n_i         : in std_logic;
    -- signal vme_bbsy_n_o         : out std_logic;
    -- signal vme_bbsy_n_dir       : out std_logic;

    -- signal vme_bclr_n_i         : in std_logic;
    -- signal vme_bclr_n_o         : out std_logic;
    -- signal vme_bclr_n_dir       : out std_logic

    ---------------------------------
    -- BUS REQUEST END           --
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    ---------------------------------
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    ---------------------------------
    -- Mini BUS REQUEST START      --
    ---------------------------------
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    -- Request bus
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    signal vme_br_n_o		: out std_logic_vector(3 downto 0);
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    -- Receive bus grant
    signal vme_bgin_n_i		: in std_logic_vector(3 downto 0);
    -- Output bus grant
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    signal vme_bgout_n_o	: out std_logic_vector(3 downto 0);
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    -- Signal bus ownership
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    signal vme_bbsy_n_o         : out std_logic;
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    -- Signal the we should clear bus
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    signal vme_bclr_n_i         : in std_logic;
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    ---------------------------------
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    -- Mini BUS REQUEST END        --
    ---------------------------------

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    ---------------------------------
    -- Serial data interface START --
    ---------------------------------

    -- signal vme_serdat_n_i         : in std_logic;
    -- signal vme_serdat_n_o         : out std_logic;
    -- signal vme_serdat_n_dir       : out std_logic

    -- signal vme_serclk_i         : in std_logic;
    -- signal vme_serclk_o         : out std_logic;
    -- signal vme_serclk_dir       : out std_logic

    -------------------------------
    -- Serial data interface END --
    -------------------------------

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    -- This is asserted when not IDLE.
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    signal busy                 : out std_logic := '0';
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    -- Latched from last VME read operation.
    -- This is valid when int_data_strobe is high.
    signal int_data_o           : out vme_vec_64_t;

    -- Strobe that indicates new data in int_data_o
    signal int_data_strobe      : out std_logic := c_DATA_CLEAR;

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    -- Strobe that indicates that the current value of
    -- int_vme_go have been consumed.
    signal int_go_consumed_strobe : out std_logic := '0';

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    -- Strobe that indicates when a BLT decision is needed.
    -- See int_blt_decided and int_blt_continue
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    signal int_blt_decision : out std_logic := '0';
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    -- Error code.
    -- Consult vme_pkg.ERR_CODE for valid values.
    -- Will be vme_pkg.ERR_CODE.OK if no problems.
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    signal int_err_code         : out err_vec_t := c_ERR_OK;    
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    signal int_addr             : in vme_addr_t;
    signal int_data_i           : in vme_vec_64_t;
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    signal int_am_i             : in am_vec_t;
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    -- signal int_vme_op           : in VME_OP;
    signal int_vme_rw           : in std_logic;
    signal int_vme_go           : in std_logic;
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    signal int_blt_decided      : in std_logic;
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    signal int_blt_continue     : in std_logic;
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    signal int_timeout_n        : in std_logic
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    );
end entity;

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architecture rtl of vme_data_bus is
  type vme_data_state is (
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    IDLE,               -- 0
    DTACK_HIGH_WAIT,    -- 1
    DTACK_LOW_WAIT,     -- 2
    AS_DELAY,           -- 3
    DS_DELAY,           -- 4
    IACK_HIGH_WAIT,     -- 5
    LATCH_DATA,         -- 6
    BLT_READ_WAIT,      -- 7
    BLT_WRITE_WAIT,     -- 8
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    IDLE_DELAY,         -- 9
    TIMEOUT,            -- 10
    TIMEOUT_WAIT        -- 11    
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    );

  type addr_type_t is (
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    A16,
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    A24,
    A32,
    ADDR_ERR
    );

  type transfer_type_t is (
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    SINGLE,             -- 0
    BLT,                -- 1
    MBLT,               -- 2
    TRANSFER_ERR        -- 3
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    );
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  signal state          : vme_data_state := IDLE;
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  signal addr_mode      : addr_type_t;
  signal transfer_mode  : transfer_type_t;
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  signal data_placed    : std_logic := '0';
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  signal n_wait      : natural range 0 to 8 := 0;
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  constant c_N_AS_DELAY  : natural range 1 to 8 :=
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    (35 / CLOCK_PERIOD);
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  constant c_N_DS_DELAY  : natural range 1 to 8 :=
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    (35 / CLOCK_PERIOD);
  constant c_N_DS_SPACING  : natural range 1 to 8 :=
    (35 / CLOCK_PERIOD);  
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  constant c_N_DATA_WAIT  : natural range 1 to 8 :=
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    (25 / CLOCK_PERIOD);
  constant c_N_TIMEOUT_WAIT  : natural range 1 to 8 :=
    (30 / CLOCK_PERIOD);

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  -- Latched signals
  signal l_addr                 : vme_addr_t;
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  signal l_rw                   : std_logic;
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  signal l_am                   : am_vec_t;
  signal l_addr_mode            : addr_type_t;
  signal l_transfer_mode        : transfer_type_t;

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  -- Latched data
  -- If READ_OP it stores the data read from slave.
  -- If WRITE_OP it stores the data to write to slave.
  signal l_data             : std_logic_vector(63 downto 0) := (others => '0');

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  signal first_cycle                  : std_logic := '1';
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  -- Timeout of operations, in order to never get stuck.
  constant TIMEOUT_CNT_MAX : integer := 255;
  signal timeout_cnt : integer range 0 to 255 := TIMEOUT_CNT_MAX;

  signal last_ds	        : std_logic_vector(1 downto 0);
  
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begin
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  -- Determine addressing mode
  with int_am_i select addr_mode <=
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    A16 when c_AM_A16 | c_AM_A16_LOCK | c_AM_A16_SUP,
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    A24 when c_AM_A24_SUP_BLT | c_AM_A24_SUP_MBLT |
    	c_AM_A24_BLT | c_AM_A24_MBLT |
    	c_AM_A24_SUP_PROG | c_AM_A24_SUP_DATA |
	c_AM_A24_PROG | c_AM_A24_DATA |
	c_AM_A24_LOCK, -- In principle correct ADDR mode
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    A32 when c_AM_A32_BLT | c_AM_A32_MBLT |
    	c_AM_A32_PROG | c_AM_A32_DATA |
	c_AM_A32_LOCK, -- In principle correct ADDR mode
    ADDR_ERR when others;

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  with int_am_i select transfer_mode <=
    SINGLE when c_AM_A32_PROG | c_AM_A32_DATA |
    	        c_AM_A24_SUP_PROG | c_AM_A24_SUP_DATA |
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	        c_AM_A24_PROG | c_AM_A24_DATA |
                c_AM_A16 | c_AM_A16_SUP,
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    BLT when c_AM_A32_BLT | c_AM_A24_SUP_BLT |
             c_AM_A24_BLT,
    MBLT when c_AM_A32_MBLT | c_AM_A24_SUP_MBLT |
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    	     c_AM_A24_MBLT,
    TRANSFER_ERR when others;

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  process (clk)
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      variable cur_data             : std_logic_vector(63 downto 0) := (others => '0');
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  begin
    if (rising_edge(clk)) then
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      -- Common delay counter
      if (n_wait /= 0) then
        n_wait <= n_wait - 1;
      end if;
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      case state is
        when IDLE =>
          -- Revert to well defined state.
          vme_addr_oe_n <= c_OE_ON;
          vme_data_oe_n <= c_OE_ON;
          vme_iackout_n_oe_n <= c_OE_OFF;
          vme_addr_dir <= c_PIN_IN;
          vme_am_dir <= c_PIN_IN;
          vme_data_dir <= c_PIN_IN;
          vme_as_n_dir <= c_PIN_IN;
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          vme_as_n_o <= '1';
          vme_berr_n_dir <= c_PIN_IN;
          vme_berr_n_o <= '1';
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          vme_iack_n_dir <= c_PIN_IN;
          vme_dtack_n_dir <= c_PIN_IN;
          vme_ds_n_dir <= c_PIN_IN;
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          vme_ds_n_o <= "11";
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          int_data_strobe <= c_DATA_CLEAR;
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          -- Munk: Retain error code until starting next cycle
          -- int_err_code <= c_ERR_OK;
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          n_wait <= 0;
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          first_cycle <= '1';
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          busy <= '0';
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          -- READ requested
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          if vme_iack_n_i = '0' then
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                state <= IACK_HIGH_WAIT;            
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          elsif (int_vme_go = '1') then
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            -- Signal that we have seen the GO
            int_go_consumed_strobe <= '1';

            if addr_mode = ADDR_ERR then
              int_err_code <= c_ERR_ADDR_MODE;
              state <= IDLE_DELAY;
            elsif transfer_mode = TRANSFER_ERR then
              int_err_code <= c_ERR_TRANSFER_MODE;
              state <= IDLE_DELAY;
            else                 
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              -- Table 2-4 and Table 2-29
              -- A[0] = LWORD*
              -- B(i) = Byte(i)
              --     | A[31-24] A[23-16] A[15-8] A[7-0] D[31-24] D[23-16] D[15-8] D[7-0]
              --   ---------------------------------------------------------------------
              -- D16 |                                                      B(0)   B(1)
              -- D32 |                                    B(0)     B(1)     B(2)   B(3)
              -- D64 |   B(0)     B(1)     B(2)   B(3)    B(4)     B(5)     B(6)   B(7)
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              l_addr <= int_addr;              
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              l_data <= int_data_i;
              l_am <= int_am_i;
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              l_rw <= int_vme_rw;
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              l_transfer_mode <= transfer_mode;
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              l_addr_mode <= addr_mode;
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              busy <= '1';
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              int_err_code <= c_ERR_OK;
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              -- Rule 2.30:
              -- The Master MUST NOT drive AS* low until IACK* has been high
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              vme_addr_o <= int_addr;
              vme_addr_dir <= c_PIN_OUT;
              vme_am_o <= int_am_i;
              vme_am_dir <= c_PIN_OUT;

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              vme_write_n_o <=  not int_vme_rw;
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              vme_iack_n_o <= '1'; -- We pull IACK* high
              vme_iack_n_dir <= c_PIN_OUT;

              -- If data lines are free then place data on them
              -- We also do this in MBLT mode.
              if (--transfer_mode /= MBLT and
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                int_vme_rw = c_VME_WRITE and
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                vme_dtack_n_i = '1')
              then
                vme_data_o <= int_data_i(31 downto 0);
                vme_data_dir <= c_PIN_OUT;
                data_placed <= '1';
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              end if;
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              n_wait <= c_N_AS_DELAY;
              state <= AS_DELAY;
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            end if;
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          end if;

        -- Rule 2.30:
        -- The Master MUST NOT drive AS* low until IACK* has been high
        -- and the required lines among A[31..1], AM[5..0], and LWORD*
        -- have been valid for this minimum time.
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        when AS_DELAY =>
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          if (n_wait = 0) then 
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            -- Signal valid address
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            vme_as_n_o <= '0';
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            vme_as_n_dir <= c_PIN_OUT;
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            int_go_consumed_strobe <= '0';
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            -- Rule 2.36:
            -- The Master MUST NOT drive DSA* low until it has driven AS* low.
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            -- Rule 2.35:
            -- The Master MUST NOT drive DSA* low until both DTACK*
            -- and BERR* are high.
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            -- Data lines free.
            if (vme_dtack_n_i & vme_berr_n_i = "11") then
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              if (l_rw = c_VME_READ) then
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                vme_ds_n_o <= "00";
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                vme_ds_n_dir <= c_PIN_OUT;

                -- Wait for slave ACK.
                state <= DTACK_LOW_WAIT;
              else
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                if (data_placed = '1') then
                  -- Data already together with addr.
                  -- We have waited enough.
                  vme_ds_n_o <= "00";
                  vme_ds_n_dir <= c_PIN_OUT;
                  data_placed <= '1';
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                  -- Wait for slave ACK.
                  state <= DTACK_LOW_WAIT;
                else
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                  -- Still in addressing phase.
                  -- We can only place data on D lines
                  vme_data_o <= l_data(31 downto 0);
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                  vme_data_dir <= c_PIN_OUT;

                  -- Rule 2.34a
                  -- During write cycles [...] the Master MUST NOT drive DSA*
                  -- low until the required lines among D[31..0] have been
                  -- valid for this minimum time.
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                  n_wait <= c_N_DS_DELAY;
                  state <= DS_DELAY;
                end if;              
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              end if;
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            else
              -- Data lines not free. We must wait.
              state <= DTACK_HIGH_WAIT;
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            end if;
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          end if;

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        -- Data bus occupied. Wait for release.
        when DTACK_HIGH_WAIT =>
          if (vme_dtack_n_i & vme_berr_n_i = "11") then
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            if (l_rw = c_VME_READ) then
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              -- Read cycle. 
              if (n_wait = 0) then
                vme_ds_n_o <= "00";
                vme_ds_n_dir <= c_PIN_OUT;
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                state <= DTACK_LOW_WAIT;
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              else
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                state <= DS_DELAY;
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              end if;              
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            else
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              -- Write cycle. Place data and wait
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              vme_data_o <= l_data(31 downto 0);
              if (l_transfer_mode = MBLT) then
                vme_addr_o <= l_data(63 downto 32);
              end if;
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              vme_data_dir <= c_PIN_OUT;

              -- Rule 2.34a
              -- During write cycles [...] the Master MUST NOT drive DSA*
              -- low until the required lines among D[31..0] have been
              -- valid for this minimum time.
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              n_wait <= c_N_DS_DELAY;
              state <= DS_DELAY;
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            end if;
          end if;

        -- Rule 2.34a
        -- During write cycles [...] the Master MUST NOT drive DSA*
        -- low until the required lines among D[31..0] have been
        -- valid for this minimum time.
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        when DS_DELAY =>
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          -- Data has been placed. Wait to drive DS.
          if (n_wait = 0) then
              vme_ds_n_o <= "00";
              vme_ds_n_dir <= c_PIN_OUT;
              state <= DTACK_LOW_WAIT;
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          end if;
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        -- Wait for slave to ack transfer
        when DTACK_LOW_WAIT =>
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          -- OBSERVATION 2.48:
          -- The Master is guaranteed that neither DTACK* nor BERR* will go low
          -- until this minimum time after it drives DSA* low.
          -- [30 ns]
          --
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          -- Munk: Thus we can only catch BERR* here.
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          -- Munk (17/8/2020) : Always catch BERR*.
          --   There might be bad modules or a bug in this code.
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          if (vme_dtack_n_i = '0') then
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            -- RULE 2.40:
            -- During all data transfer cycles, excluding A16, A24 and A32
            -- Read-Modify-Write and Retry cycles, the Master MUST drive A[31..1] and LWORD*
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            -- with valid addressing information until it detects the first_cycle falling edge
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            -- on DTACK* or BERR*.

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            if (l_rw = c_VME_READ) then
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              -- Munk: We can thus always flip dir on ADDR pins.
              -- This simplifies MBLT logic
              vme_addr_dir <= c_PIN_IN;
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              if l_transfer_mode = MBLT and first_cycle = '1' then
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                vme_ds_n_o <= "11";
                n_wait <= c_N_DS_SPACING; -- 40ns cooldown of DS*               
                state <= DTACK_HIGH_WAIT;
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              else                
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                n_wait <= c_N_DATA_WAIT;
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                state <= LATCH_DATA;
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              end if;
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            else
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              -- Rescind DS*
              vme_ds_n_o <= "11";
              case l_transfer_mode is
                when SINGLE =>
                  -- We are done. Terminate cycle and IDLE.
                  vme_as_n_o <= '1';
                  state <= IDLE;
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                  busy <= '0';
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                  int_data_strobe <= c_DATA_PRESENT;
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                  int_err_code <= c_ERR_OK;
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                when BLT =>
                  -- Per Rule 2.34a there must be 40ns delay
                  -- between DS* transistions. Handle this in next cycle
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                  int_blt_decision <= '1';
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                  int_data_strobe <= c_DATA_PRESENT;
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                  state <= BLT_WRITE_WAIT;
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                when MBLT =>
                  if first_cycle = '0' then
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                    int_blt_decision <= '1';
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                    int_data_strobe <= c_DATA_PRESENT;
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                    state <= BLT_WRITE_WAIT;
                  else
                    -- ADDR broadcast. Now write data.
                    n_wait <= c_N_DS_SPACING; -- 40ns cooldown of DS*               
                    state <= DTACK_HIGH_WAIT;
                  end if;                  
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                when others =>
                  assert false report "not implemented!";
              end case;              
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            end if;
            first_cycle <= '0';
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          end if;
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        -- OBSERVATION 2.47a:
        -- During read cycles, the Master is guaranteed that D[31..0] will be
        -- valid within 25 nanoseconds after DTACK* goes low. In addition, during
        -- MBLT, A40BLT, and MD32 read cycles, the Master is guaranteed that A[31..1]
        -- and LWORD* will be valid within 25 nanoseconds after DTACK* goes low.
        -- This time does not apply to cycles where the Slave drives BERR* low instead
        -- of DTACK*.          
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        when LATCH_DATA =>
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          -- Table 2-4 and Table 2-29
          -- A[0] = LWORD*
          -- B(i) = Byte(i)
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          -- B(0) is the most significant byte
          --
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          --     | A[31-24] A[23-16] A[15-8] A[7-0] D[31-24] D[23-16] D[15-8] D[7-0]
          --   ---------------------------------------------------------------------
          -- D16 |                                                      B(0)   B(1)
          -- D32 |                                    B(0)     B(1)     B(2)   B(3)
          -- D64 |   B(0)     B(1)     B(2)   B(3)    B(4)     B(5)     B(6)   B(7)
          --
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          -- Conclusion:
          -- The D lines always carry the least significant bits.
          -- If we run MBLT then the A lines with carry the MSB.
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          -- 
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          cur_data(31 downto 0) := vme_data_i;
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          case l_transfer_mode is
            when SINGLE | BLT =>
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              -- l_data(31 downto 0) => vme_data_i;
              cur_data(63 downto 32) := (others => '0');
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            when MBLT =>
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              -- l_data(31 downto 0) => vme_addr_i;
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              cur_data(63 downto 32) := vme_addr_i;
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            when others =>
              assert false report "Logic error!";
          end case;
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          -- Munk: In principle we can have cur_data = l_data,
          -- first time n_wait = 0.
          -- In this case l_data is latched when n_wait = 1.
          -- Howver, according to observation 2.47a, then data is
          -- valid WITHIN 25ns. 
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          if (n_wait = 0) then
            -- Latched data stable
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            if (cur_data = l_data) then
              -- Slave only maintains data lines while
              -- DS* asserted. They can be deasserted now. 
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              vme_ds_n_o <= "11";
              vme_ds_n_dir <= c_PIN_OUT;
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              int_data_o <= cur_data;
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              int_data_strobe <= c_DATA_PRESENT;

              case l_transfer_mode is
                when SINGLE =>
                  vme_as_n_o <= '1';
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                  state <= IDLE;
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                  busy <= '0';
                  int_err_code <= c_ERR_OK;
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                when BLT | MBLT =>
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                  n_wait <= c_N_DS_SPACING;
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                  int_blt_decision <= '1';
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                  state <= BLT_READ_WAIT;
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                when others =>
                  assert false report "Logic error!";
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              end case;              
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            else -- Unstable data. Try again
              n_wait <= 1;
            end if;
          end if;
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          l_data <= cur_data;

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        when BLT_WRITE_WAIT =>
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          int_data_strobe <= c_DATA_CLEAR;
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          if int_blt_decided = '1' then
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            int_blt_decision <= '0';
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            if int_blt_continue = '1' then
              l_data <= int_data_i; -- Latch new data
              state <= DTACK_HIGH_WAIT; -- Wait for slave to rescind DTACK
            else
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              -- Terminate cycle
              vme_as_n_o <= '1';
              state <= IDLE;
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              busy <= '0';
              int_err_code <= c_ERR_OK;
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            end if;
          end if;                    
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        when BLT_READ_WAIT =>
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          int_data_strobe <= c_DATA_CLEAR;
          if int_blt_decided = '1' then            
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            int_blt_decision <= '0';
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            if int_blt_continue = '1' then          
              state <= DTACK_HIGH_WAIT;
            else
              -- Block transfer is terminated by AS* high.
              vme_as_n_o <= '1';
              n_wait <= 0;
              state <= IDLE;
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              busy <= '0';
              int_err_code <= c_ERR_OK;
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            end if;
          end if;
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        when IACK_HIGH_WAIT =>
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          if vme_iack_n_i = '1' then
            state <= IDLE;
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          end if;
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          -- Note: this state does not assert busy, since we
          -- are not working on behalf of the client.
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        -- Delay return to IDLE.          
        when IDLE_DELAY =>
          state <= IDLE;
          busy <= '0';
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        -- Timeout!  Something is preventing the state machine
        -- from completing.  Either an external error (e.g. a
        -- non-responding module), or a bug in this code.

        -- BERR is issued and we stop driving signals.
        when TIMEOUT =>
          vme_berr_n_dir <= c_PIN_OUT;
          vme_berr_n_o <= '0';
          
          vme_ds_n_dir <= c_PIN_IN;
          vme_ds_n_o <= "11";
          
          vme_as_n_dir <= c_PIN_IN;
          vme_as_n_o <= '1';

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          vme_dtack_n_dir <= c_PIN_IN;

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          -- Data present (error)
          int_data_strobe <= c_DATA_PRESENT;
          int_err_code <= (
            c_ERR_BERR_I => not vme_berr_n_i,
            c_ERR_TIMEOUT_I => '1',
            others => '0'
            );
          busy <= '0';
          -- Attempt to leave the TIMEOUT state
          n_wait <= c_N_TIMEOUT_WAIT;
          state <= TIMEOUT_WAIT;


        -- We stay here and wait 
        when TIMEOUT_WAIT =>
          -- Make sure that also noone else is driving
          -- AS, DS or DTACK before we consider leaving
          -- TIMEOUT state.

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          if (vme_ds_n_i = "00" or
              vme_as_n_i = '0' or
              vme_dtack_n_i = '0') then
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            -- Someone is still holding a strobe.
            n_wait <= c_N_TIMEOUT_WAIT;
          elsif (n_wait = 0) then
            vme_berr_n_o <= '1';
            vme_berr_n_dir <= c_PIN_IN;
            state <= IDLE;
          end if;
      end case;

      -- This is after state machine, such that it can force
      -- into TIMEOUT state, no matter what happens.
      -- Also an seemingly indefinate wait in IACK_HIGH_WAIT
      -- will be cut short, such that we report failure to
      -- perform the access to our superiors.

      -- VME spec 2.37:
      -- [...]
      -- The Master, upon completing the first data transfer,
      -- (that is, driving the data strobes high) does not allow
      -- the address strobe to go high. Instead, it repeatedly
      -- drives the data strobe(s) low in response to data transfer
      -- acknowledgments from the Slave
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      last_ds <= vme_ds_n_i;
      if (last_ds /= vme_ds_n_i or -- 
          state    = IDLE or
          state    = IDLE_DELAY or
          state    = TIMEOUT or
          state    = TIMEOUT_WAIT) then
        -- Things are good, or we have fired (no need to fire again).
        timeout_cnt <= TIMEOUT_CNT_MAX;
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      elsif (vme_berr_n_i & int_timeout_n /= "11") then
        state <= TIMEOUT;
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      elsif (timeout_cnt = 0) then
        -- We have been operating for too long, timeout.
        state <= TIMEOUT;
      else
        timeout_cnt <= timeout_cnt - 1;
      end if;
      
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    end if;
  end process;


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  FormalG : if Formal generate

    -- VHDL helper vars
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    signal f_addr               : std_logic_vector(31 downto 0) := (others => 'U');
    signal f_data               : std_logic_vector(63 downto 0) := (others => 'U');        
    signal f_latch_data2        : std_logic_vector(63 downto 0) := (others => 'U');    
    signal f_latch_data         : std_logic_vector(63 downto 0) := (others => 'U');
    signal f_blt_data           : std_logic_vector(63 downto 0) := (others => 'U');    
    signal f_am                 : am_vec_t := (others => 'U');
    signal f_berr_ok            : std_logic := 'U';
    signal f_vme_rw             : std_logic := 'U';
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    signal f_blt_cycle          : integer := 0;
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  begin

    process (clk) begin
      if (rising_edge(clk)) then
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        if (state = IDLE and int_vme_go = '1') then
          f_addr <= int_addr;
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          f_am <= int_am_i;
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          f_vme_rw <= int_vme_rw;
          f_data <= int_data_i;
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        end if;

        if (state = LATCH_DATA) then
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          f_latch_data2 <= f_latch_data;
          f_latch_data(31 downto 0) <= vme_data_i;
          f_latch_data(63 downto 32) <= vme_addr_i;
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        end if;
        
        
        -- Data latched during BLT continue op
        if (state = BLT_WRITE_WAIT
            and int_blt_decided = '1' and int_blt_continue = '1')
        then
          f_blt_data <= int_data_i;
        end if;

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        if (state = IDLE) then
          f_blt_cycle <= 0;
        elsif (state = BLT_WRITE_WAIT) then
          f_blt_cycle <= f_blt_cycle + 1;
        end if;
        

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      end if;
    end process;

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    -- psl default clock is rising_edge(clk);
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    -- psl restrict {{vme_iack_n_i = '1' and vme_berr_n_i = '1'}[+]};

    -- -- Check that client input is latched
    -- psl when_go_addr_is_latched:
    --   assert always {int_vme_go = '1'
    --                  and transfer_mode /= TRANSFER_ERR
    --                  and addr_mode /= ADDR_ERR}
    --     |=> l_addr = f_addr until busy = '0';

    -- psl when_go_am_is_latched:
    --   assert always {int_vme_go = '1'
    --                  and transfer_mode /= TRANSFER_ERR
    --                  and addr_mode /= ADDR_ERR}
    --     |=> l_am = f_am until busy = '0';

    -- psl when_go_rw_is_latched:
    --   assert always {int_vme_go = '1'
    --                  and transfer_mode /= TRANSFER_ERR
    --                  and addr_mode /= ADDR_ERR}
    --     |=> l_rw = f_vme_rw until busy = '0';

    -- -- We only check data next cycle.
    -- -- This might be relatched
    -- psl when_go_data_is_latch:
    --   assert always {state = IDLE and int_vme_go = '1'
    --                  and transfer_mode /= TRANSFER_ERR
    --                  and addr_mode /= ADDR_ERR}
    --     |=> l_data = f_data;    

    -- -- Maintain BUSY until back in IDLE
    -- psl core_is_busy_until_idle:
    --   assert always {state = IDLE; int_vme_go = '1'
    --                  and transfer_mode /= TRANSFER_ERR
    --                  and addr_mode /= ADDR_ERR}
    --     |=> busy = '1' until state = IDLE;

    -- psl when_unsupported_addr_mode_issue_error_code:
    --   assert always {state = IDLE and int_vme_go = '1' and addr_mode = ADDR_ERR}
    --     |=> int_err_code = c_ERR_ADDR_MODE
    --     and state = IDLE_DELAY;

    -- psl when_unsupported_transfer_mode_issue_error_code:
    --   assert always {state = IDLE and int_vme_go = '1'
    --                  and transfer_mode = TRANSFER_ERR
    --                  and addr_mode /= ADDR_ERR}
    --     |=> int_err_code = c_ERR_TRANSFER_MODE
    --     and state = IDLE_DELAY;        

    -- -- If DTACK* is LOW after AS_DELAY,
    -- -- then we must wait for data lines to clear.
    -- psl core_will_not_start_until_dtack_high:
    --   assert always {vme_dtack_n_i = '0' and state = AS_DELAY and n_wait=0}
    --     |=> state = DTACK_HIGH_WAIT until vme_dtack_n_i = '1';

    -- -- We maintain go_consumed high until end of AS_DELAY
    -- psl go_consumed_is_signalled_until_as_delay:
    --   assert always {state = IDLE and int_vme_go = '1'}
    --     |=> int_go_consumed_strobe = '1' until state /= AS_DELAY;

    -- -- Don't fire AS* during AS_DELAY
    -- psl addr_strobe_are_not_fired_during_as_delay:
    --   assert always {state = AS_DELAY}
    --     |=> vme_as_n_o = '1' and vme_as_n_dir = c_PIN_IN
    --     until state /= AS_DELAY;

    -- -- AS* fires after we leave AS_DELAY
    -- psl addr_strobe_are_fired_after_as_delay:
    --   assert always {state = AS_DELAY and n_wait = 0}
    --     |=> vme_as_n_o = '0' and vme_as_n_dir = c_PIN_OUT;

    -- -- AS* fires after we leave AS_DELAY
    -- psl if_dtack_is_asserted_in_as_then_we_wait_until_deasserted:
    --   assert always {state = AS_DELAY and n_wait = 0 and vme_dtack_n_i = '0'}
    --     |=> state = DTACK_HIGH_WAIT and vme_ds_n_o = "11"
    --     until vme_dtack_n_i = '1';    

    -- -- Don't fire DS* during AS_DELAY
    -- psl data_strobes_are_not_fired_during_as_delay:
    --   assert always {state = AS_DELAY}
    --     |=> vme_ds_n_o = "11" and vme_ds_n_dir = c_PIN_IN
    --     until state /= AS_DELAY;

    -- psl data_strobe_are_fired_with_as_when_data_placed:
    --   assert always {vme_dtack_n_i = '1' and
    --                  state = AS_DELAY and l_rw = c_VME_WRITE
    --                  and data_placed = '1' and n_wait = 0}
    --     |=> vme_ds_n_o = "00";

    -- -- If writing and waiting for DTACK* HIGH,
    -- -- then data is placed when satisfied.
    -- psl when_writing_and_dtack_fires_place_data:
    --   assert always {l_transfer_mode = SINGLE
    --                  and l_rw = c_VME_WRITE
    --                  and state = DTACK_HIGH_WAIT; vme_dtack_n_i = '1'}
    --     |=> vme_data_o = l_data(31 downto 0);

    -- -- If IDLE and GO given
    -- -- and data lines are free (DTACK* = 1)
    -- -- and we are writing.
    -- -- Then place low 32 bits immideately 
    -- psl when_writing_and_dtack_is_high_then_data_is_placed:
    --   assert always {int_vme_go = '1' and state = IDLE
    --                  and int_vme_rw = c_VME_WRITE and vme_dtack_n_i = '1'
    --                  and int_am_i = c_AM_A24_DATA}
    --     |=> vme_data_o = l_data(31 downto 0)
    --     until state = DTACK_LOW_WAIT or state = IDLE;

    -- -- When writing MBLT the data will be placed on the bus
    -- psl mblt_writing_data_is_placed_on_bus:
    --   assert always {state = DTACK_HIGH_WAIT and l_transfer_mode = MBLT
    --                  and first_cycle = '1' and vme_dtack_n_i = '1'
    --                  and l_rw = c_VME_WRITE}
    --     |=> vme_data_o = l_data(31 downto 0)
    --     and vme_addr_o = l_data(63 downto 32);

    -- -- When writing MBLT the data latched during BLT_WRITE_WAIT
    -- -- is written to both addr and data pins
    -- psl mblt_writing_data_is_placed_on_bus_second_time:
    --   assert always {state = DTACK_HIGH_WAIT and l_transfer_mode = MBLT
    --                  and first_cycle = '0' and vme_dtack_n_i = '1'
    --                  and l_rw = c_VME_WRITE and f_blt_cycle > 0}
    --     |=> vme_data_o = f_blt_data(31 downto 0)
    --     and vme_addr_o = f_blt_data(63 downto 32);            

    -- -- If stopping BLT write transaction,
    -- -- then return to IDLE
    -- psl return_to_idle_if_stopping_blt_write:
    --   assert always {state = BLT_WRITE_WAIT
    --                  and int_blt_decided = '1' and int_blt_continue = '0'}
    --     |=> state = IDLE;

    -- -- If stopping BLT read transaction,
    -- -- then return to IDLE
    -- psl return_to_idle_if_stopping_blt_read:
    --   assert always {state = BLT_READ_WAIT
    --                  and int_blt_decided = '1' and int_blt_continue = '0'}
    --     |=> state = IDLE;

    -- -- When latching 32 or 16 bit data,
    -- -- then low 32 bits are from data lines
    -- -- and high 32 bits are set to 0.
    -- psl data_is_latched_when_stable:
    --   assert always {state = LATCH_DATA and n_wait = 0
    --                  and f_latch_data = f_latch_data2 and l_transfer_mode /= MBLT}
    --     |-> l_data(31 downto 0) = f_latch_data(31 downto 0)
    --     and l_data(63 downto 32) = "00000000000000000000000000000000";

    -- -- When latching 64 bit data,
    -- -- then low 32 bits are from data lines
    -- -- and high 32 bits are from addr lines.    
    -- psl mblt_data_is_latched_when_stable:
    --   assert always {state = LATCH_DATA
    --                  and f_latch_data = f_latch_data2 and l_transfer_mode = MBLT;
    --                  n_wait = 0}
    --     |-> l_data(31 downto 0) = f_latch_data(31 downto 0)
    --     and l_data(63 downto 32) = f_latch_data(63 downto 32); 
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    -- -- If BLT write is continued,
    -- -- then new data is latched.
    -- psl if_continueing_blt_write_then_latch_new_data:
    --   assert always {state = BLT_WRITE_WAIT
    --                  and int_blt_decided = '1' and int_blt_continue = '1'}
    --     |=> l_data = f_blt_data;    
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  end generate FormalG;
  
  
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end architecture;
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