tb_vme_bus.vhd 31 KB
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library vunit_lib;
context vunit_lib.vunit_context;

library ieee;
use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.vme_pkg.all;
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entity tb_vme_bus is
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  generic (runner_cfg : string);
end entity;

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architecture tb of tb_vme_bus is
  signal clk    : std_logic := '0';

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  signal vme_addr_i		: std_logic_vector(31 downto 0);
  signal vme_addr_o		: std_logic_vector(31 downto 0);
  signal vme_addr_dir		: std_logic;
  signal vme_addr_oe_n	: std_logic;

  signal vme_am_i		: am_vec_t;
  signal vme_am_o		: am_vec_t;
  signal vme_am_dir		: std_logic;
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--    signal vme_am_oe_n	: std_logic -- Shared with addr
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  signal vme_write_n_i        : std_logic;
  signal vme_write_n_o        : std_logic;
  -- write shares DIR and OE with AM

  signal vme_data_i		: std_logic_vector(31 downto 0);
  signal vme_data_o		: std_logic_vector(31 downto 0);
  signal vme_data_dir		: std_logic;
  signal vme_data_oe_n	: std_logic;

  signal vme_as_n_i		: std_logic;
  signal vme_as_n_o		: std_logic;
  signal vme_as_n_dir		: std_logic;

  signal vme_iack_n_i		: std_logic;
  signal vme_iack_n_o		: std_logic;
  signal vme_iack_n_dir	: std_logic;

  -- Always enabled, always input
  signal vme_iackin_n		: std_logic;

  -- Enable IACKOUT_n. Will be pulled low 
  signal vme_iackout_n_oe_n	: std_logic;    

  signal vme_dtack_n_i	: std_logic;
  signal vme_dtack_n_o	: std_logic;
  signal vme_dtack_n_dir	: std_logic;

  signal vme_ds_n_i	        : std_logic_vector(1 downto 0);
  signal vme_ds_n_o	        : std_logic_vector(1 downto 0);
  signal vme_ds_n_dir	        : std_logic;

  signal vme_berr_n_i         : std_logic;
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  signal vme_berr_n_o         : std_logic;
  signal vme_berr_n_dir         : std_logic;  
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  -- Request bus
  signal vme_br_n_o		: std_logic_vector(3 downto 0);
  -- Receive bus grant
  signal vme_bgin_n_i		: std_logic_vector(3 downto 0);
  -- Output bus grant
  signal vme_bgout_n_o	: std_logic_vector(3 downto 0);
  -- Signal bus ownership
  signal vme_bbsy_n_o         : std_logic;
  -- Signal the we should clear bus
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  signal vme_bclr_n_i         : std_logic;
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  signal busy                   : std_logic;
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  signal int_addr             : std_logic_vector(31 downto 0);
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  signal int_data_i           : std_logic_vector(63 downto 0);
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  signal int_data_o           : std_logic_vector(63 downto 0);
  signal int_am_i             : am_vec_t;
  
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  signal int_vme_write            : std_logic;
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  signal int_vme_go            : std_logic := '1';  
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  signal int_data_strobe        : std_logic;
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  signal int_blt_decided        : std_logic := '0';
  signal int_blt_continue       : std_logic := '0';  
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  signal int_berr_ok            : std_logic := '0';
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  signal int_err_code           : err_vec_t;
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  signal int_err_clear          : std_logic := '0';

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begin
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  main: process
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  begin
    test_runner_setup(runner, runner_cfg);

    while test_suite loop

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      if run("output pin = 1") then
        check_equal(c_PIN_OUT, '1');
      elsif run("output pin = 0") then
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        check_equal(c_PIN_IN, '0');
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      elsif run("VME bus starts in well defined state") then     
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        -- ds default to input mode") 
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        check_equal(vme_ds_n_dir, c_PIN_IN);
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        -- as default to input mode") 
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        check_equal(vme_as_n_dir, c_PIN_IN);        
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        -- iack default to input mode") 
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        check_equal(vme_iack_n_dir, c_PIN_IN);
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        -- data default to input mode") 
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        check_equal(vme_data_dir, c_PIN_IN);
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        -- am default to input mode") 
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        check_equal(vme_am_dir, c_PIN_IN);
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        -- addr default to input mode") 
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        check_equal(vme_addr_dir, c_PIN_IN);
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        -- addr default to high Z") 
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        check_equal(vme_addr_oe_n, c_OE_OFF);
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        -- data default to high Z") 
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        check_equal(vme_data_oe_n, c_OE_OFF);
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        -- iack out defaults to high Z") 
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        check_equal(vme_iackout_n_oe_n, c_OE_OFF);

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        check_equal(int_err_code, c_ERR_OK);
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      elsif run("when VME bus is started OE turns low") then
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        wait for 20 ns;
        check_equal(vme_addr_oe_n, c_OE_ON);
        check_equal(vme_data_oe_n, c_OE_ON);

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      elsif run("in regular A24 mode the addr is output") then
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        int_am_i <= c_AM_A24_DATA;
        int_addr <= (others => '1');
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        wait for 20 ns;
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        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
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--        check_equal(int_cur_state, '0');
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      elsif run("in regular A32 mode the addr is output") then
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        int_am_i <= c_AM_A32_DATA;
        int_addr <= (others => '1');
            
        wait for 20 ns;
        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);        

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      elsif run("AS* is delayed >= 35ns compared to ADDR") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_go <= '1';
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        int_vme_write <= c_VME_READ;
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        int_am_i <= c_AM_A24_DATA;
        int_addr <= (others => '1');
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        wait for 20 ns;
        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        
        check_equal(vme_as_n_dir, c_PIN_IN);        
        wait for 10 ns;
        check_equal(vme_as_n_dir, c_PIN_IN);
        wait for 10 ns;
        check_equal(vme_as_n_dir, c_PIN_IN);
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        wait for 10 ns;        
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        check_equal(vme_as_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"00"));
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      elsif run("DS* is delayed until DTACK* clear") then     
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        vme_dtack_n_i <= '0';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_READ;        
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        int_am_i <= c_AM_A24_DATA;
        int_addr <= (others => '1');
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        wait for 20 ns;
        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        
        check_equal(vme_as_n_dir, c_PIN_IN);        
        wait for 40 ns;
        check_equal(vme_as_n_dir, c_PIN_OUT);
        check_equal(vme_ds_n_dir, c_PIN_IN);
        wait for 20 ns;
        check_equal(vme_ds_n_dir, c_PIN_IN);

        vme_dtack_n_i <= '1';
        
        wait for 15 ns;
        check_equal(vme_ds_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"00"));
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      elsif run("if WRITE=1 and DTACK*=1 then data is placed together with ADDR") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_WRITE;
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        int_am_i <= c_AM_A24_DATA;
        int_addr <= (others => '1');
        int_data_i <= (others => '1');
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        wait for 20 ns;
        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        check_equal(vme_data_dir, c_PIN_OUT);
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        check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0));
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      elsif run("if SiCy WRITE and slave ack then FSM => IDLE") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_WRITE;
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        int_am_i <= c_AM_A24_DATA;
        int_addr <= (others => '1');
        int_data_i <= (others => '1');
        
        wait for 20 ns;
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        int_vme_go <= '0';
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        check_equal(int_err_code, c_ERR_OK);
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        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        check_equal(vme_data_dir, c_PIN_OUT);
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        check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0));
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        wait for 40 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"00"));
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        check_equal(vme_as_n_o, '0');                
        
        -- Slave ack
        vme_dtack_n_i <= '0';
        wait for 10 ns;
        -- Rescind AS* and DS*
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        check_equal(vme_as_n_o, '1');
        wait for 10 ns;
        check_equal(vme_addr_dir, c_PIN_IN);
        check_equal(vme_am_dir, c_PIN_IN);
        check_equal(busy, '0');             
        
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      elsif run("if data is placed together with ADDR then DS fires with AS") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_WRITE;
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        int_am_i <= c_AM_A24_DATA;
        int_addr <= (others => '1');
        int_data_i <= (others => '1');
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        wait for 20 ns;
        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        check_equal(vme_data_dir, c_PIN_OUT);
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        check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0));
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        check_equal(vme_as_n_dir, c_PIN_IN);        
        wait for 40 ns;
        check_equal(vme_as_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"00"));        
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      elsif run("if data is not placed together with ADDR then DS is delayed") then     
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        vme_dtack_n_i <= '0';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_WRITE;
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        int_am_i <= c_AM_A24_DATA;
        int_addr <= (others => '1');
        int_data_i <= (others => '1');
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        wait for 20 ns;
        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
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        check_equal(vme_data_dir, c_PIN_IN);
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        check_equal(vme_as_n_dir, c_PIN_IN);        
        wait for 60 ns;
        check_equal(vme_as_n_dir, c_PIN_OUT);
        check_equal(vme_data_dir, c_PIN_IN);
        
        vme_dtack_n_i <= '1';
        
        wait for 15 ns;
        check_equal(vme_data_dir, c_PIN_OUT);
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        check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0));
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        check_equal(vme_ds_n_dir, c_PIN_IN);
        
        wait for 45 ns;
        check_equal(vme_ds_n_dir, c_PIN_OUT);
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      elsif run("DS* is released when DTACK* received") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_READ;
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        int_am_i <= c_AM_A24_DATA;
        int_addr <= (others => '1');
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        vme_data_i <= (others => '1');
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        wait for 20 ns;
        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        
        check_equal(vme_as_n_dir, c_PIN_IN);        
        wait for 40 ns;
        check_equal(vme_ds_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"00"));
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        -- Slave ACK
        vme_dtack_n_i <= '0';
        vme_data_i <= (others => '1');
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        check_equal(int_data_strobe, c_DATA_CLEAR);
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        wait for 10 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"00"));
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        wait for 50 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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      elsif run("DS* is released after write when DTACK* received") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_WRITE;
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        int_am_i <= c_AM_A24_DATA;
        int_addr <= (others => '1');
        vme_data_i <= (others => '1');
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        wait for 20 ns;
        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        
        check_equal(vme_as_n_dir, c_PIN_IN);        
        wait for 40 ns;
        check_equal(vme_ds_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"00"));
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        -- Slave ACK
        vme_dtack_n_i <= '0';
        vme_data_i <= (others => '1');
        check_equal(int_data_strobe, c_DATA_CLEAR);
        wait for 10 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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      elsif run("AS* is pulled high after regular reads") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_READ;
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        int_am_i <= c_AM_A24_DATA;
        int_addr <= (others => '0');
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        wait for 20 ns;
        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        
        check_equal(vme_as_n_dir, c_PIN_IN);        
        wait for 40 ns;
        check_equal(vme_ds_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"00"));
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        -- Slave ACK
        vme_dtack_n_i <= '0';
        vme_data_i <= (others => '1');
        
        check_equal(int_data_strobe, c_DATA_CLEAR);
        wait for 10 ns;
        wait for 30 ns;
        check_equal(vme_as_n_o, '1');

      elsif run("Data is presented to clients after regular reads") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_READ;
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        int_am_i <= c_AM_A24_DATA;
        int_addr <= (others => '0');
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        wait for 60 ns;

        -- Slave ACK
        vme_dtack_n_i <= '0';
        vme_data_i <= (others => '1');
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        check_equal(int_data_strobe, c_DATA_CLEAR);
        wait for 40 ns;
        check_equal(int_data_strobe, c_DATA_PRESENT);
        check_equal(int_data_o(31 downto 0), vme_data_i(31 downto 0));

      elsif run("During regular reads, when clients signal data read, FSM => IDLE") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_READ;
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        int_am_i <= c_AM_A24_DATA;
        int_addr <= (others => '0');
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        wait for 60 ns;

        -- Slave ACK
        vme_dtack_n_i <= '0';
        vme_data_i <= (others => '1');
        
        check_equal(int_data_strobe, c_DATA_CLEAR);
        wait for 40 ns;
        check_equal(int_data_strobe, c_DATA_PRESENT);
        wait for 10 ns;
        check_equal(int_data_strobe, c_DATA_CLEAR);
        
        check_equal(vme_addr_oe_n, c_OE_ON);
        check_equal(vme_data_oe_n, c_OE_ON);
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      elsif run("if doing BLT read and int_blt_op = BLT_CONTINUE then BLT continues") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_READ;
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        int_am_i <= c_AM_A24_BLT;
        int_addr <= (others => '0');
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        wait for 60 ns;

        -- Slave ACK
        vme_dtack_n_i <= '0';
        vme_data_i <= (others => '1');
        
        check_equal(int_data_strobe, c_DATA_CLEAR);
        wait for 40 ns;
        check_equal(int_data_strobe, c_DATA_PRESENT);
        check_equal(vme_ds_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        vme_dtack_n_i <= '1';
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        int_blt_decided <= '1'; int_blt_continue <= '1';
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        wait for 10 ns;
        check_equal(int_data_strobe, c_DATA_CLEAR);
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        wait for 10 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        wait for 10 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        wait for 10 ns;        
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        check_equal(vme_ds_n_o, unsigned'(B"00"));
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      elsif run("if doing BLT read and int_blt_op = BLT_STOP then BLT stops") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_READ;
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        int_am_i <= c_AM_A24_BLT;
        int_addr <= (others => '0');
        
        wait for 60 ns;

        -- Slave ACK
        vme_dtack_n_i <= '0';
        vme_data_i <= (others => '1');
        
        check_equal(int_data_strobe, c_DATA_CLEAR);
        wait for 40 ns;
        check_equal(int_data_strobe, c_DATA_PRESENT);
        check_equal(vme_ds_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        vme_dtack_n_i <= '1';
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        int_blt_decided <= '1'; int_blt_continue <= '0';
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        wait for 10 ns;
        check_equal(int_data_strobe, c_DATA_CLEAR);
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        check_equal(vme_as_n_o, '1');        


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      elsif run("if continuing BLT then DS* will wait for DTACK* high again") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_READ;
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        int_am_i <= c_AM_A24_BLT;
        int_addr <= (others => '0');
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        wait for 60 ns;

        -- Slave ACK
        vme_dtack_n_i <= '0';
        vme_data_i <= (others => '1');
        
        wait for 40 ns;
        check_equal(int_data_strobe, c_DATA_PRESENT);
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        check_equal(int_data_o(31 downto 0), vme_data_i(31 downto 0));        
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        check_equal(vme_ds_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        int_blt_decided <= '1'; int_blt_continue <= '1';
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        wait for 10 ns;
        check_equal(int_data_strobe, c_DATA_CLEAR);
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        wait for 40 ns;        
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        vme_dtack_n_i <= '1';
        wait for 10 ns;        
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        check_equal(vme_ds_n_o, unsigned'(B"00"));
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      elsif run("if continuing BLT then data is latched when DTACK goes low again") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_READ;
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        int_am_i <= c_AM_A24_BLT;
        int_addr <= (others => '0');
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        wait for 60 ns;

        -- Slave ACK
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        vme_dtack_n_i <= '0';
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        vme_data_i <= (others => '1');
        
        wait for 40 ns;
        check_equal(int_data_strobe, c_DATA_PRESENT);
        check_equal(int_data_o(31 downto 0), vme_data_i(31 downto 0));        
        check_equal(vme_ds_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        int_blt_decided <= '1'; int_blt_continue <= '1';
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        wait for 10 ns;
        check_equal(int_data_strobe, c_DATA_CLEAR);
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        wait for 30 ns;        
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        vme_dtack_n_i <= '1';
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        wait for 10 ns;        
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        check_equal(vme_ds_n_o, unsigned'(B"00"));
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        vme_dtack_n_i <= '0';
        vme_data_i <= (others => '0');
        wait for 40 ns;
        check_equal(int_data_strobe, c_DATA_PRESENT);
        check_equal(int_data_o(31 downto 0), vme_data_i(31 downto 0));                

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      elsif run("ADDR lines are released when DTACK* received in MBLT mode") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_READ;
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        int_am_i <= c_AM_A24_MBLT;
        int_addr <= (others => '1');
        vme_data_i <= (others => '1');
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        wait for 20 ns;
        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        
        check_equal(vme_as_n_dir, c_PIN_IN);        
        wait for 40 ns;
        check_equal(vme_ds_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"00"));
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        -- Slave ACK
        vme_dtack_n_i <= '0';
        vme_data_i <= (others => '1');
        check_equal(int_data_strobe, c_DATA_CLEAR);
        wait for 50 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        check_equal(vme_addr_dir, c_PIN_IN);

      elsif run("Data is not latched during first MBLT cycle") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_READ;
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        int_am_i <= c_AM_A24_MBLT;
        int_addr <= (others => '1');
        vme_data_i <= (others => '1');
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        wait for 20 ns;
        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
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        check_equal(vme_as_n_dir, c_PIN_IN);        
        wait for 40 ns;
        check_equal(vme_ds_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"00"));
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        -- Slave ACK
        vme_dtack_n_i <= '0';
        vme_data_i <= (others => '1');
        check_equal(int_data_strobe, c_DATA_CLEAR);
        wait for 50 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        check_equal(vme_addr_dir, c_PIN_IN);
        check_equal(int_data_strobe, c_DATA_CLEAR);

      elsif run("MBLT data is latched after second DTACK low") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_READ;
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        int_am_i <= c_AM_A24_MBLT;
        int_addr <= (others => '1');
        vme_data_i <= (others => '1');
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        wait for 20 ns;
        wait for 40 ns;

        -- Slave ACK
        vme_dtack_n_i <= '0';
        vme_data_i <= (others => '1');
        check_equal(int_data_strobe, c_DATA_CLEAR);
        wait for 10 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        check_equal(vme_addr_dir, c_PIN_IN);
        check_equal(int_data_strobe, c_DATA_CLEAR);

        vme_dtack_n_i <= '1';

        -- DS* edges must be spaced by 40 ns
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        wait for 10 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        wait for 10 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        wait for 10 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"11"));        
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        wait for 10 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"00"));
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        -- Slave signals data
        vme_dtack_n_i <= '0';
        wait for 40 ns;
        check_equal(int_data_strobe, c_DATA_PRESENT);
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      elsif run("for MBLT write data is placed on D and A lines after slave ack") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_WRITE;
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        int_am_i <= c_AM_A24_MBLT;
        int_addr <= (others => '0');
        int_data_i <= (others => '1');
        
        wait for 20 ns;
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        check_equal(int_err_code, c_ERR_OK);
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        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        
        check_equal(vme_as_n_dir, c_PIN_IN);        
        wait for 40 ns;
        check_equal(vme_ds_n_dir, c_PIN_OUT);
        check_equal(vme_ds_n_o, unsigned'(B"00"));

        -- Slave ACK
        vme_dtack_n_i <= '0';
        check_equal(int_data_strobe, c_DATA_CLEAR);
        wait for 10 ns;
        -- DS* flip
        check_equal(vme_ds_n_o, unsigned'(B"11"));
        vme_dtack_n_i <= '1';
        -- DS* delay
        wait for 50 ns;
        check_equal(vme_ds_n_o, unsigned'(B"00"));

        check_equal(vme_data_o, unsigned'(B"11111111111111111111111111111111"));
        check_equal(vme_addr_o, unsigned'(B"11111111111111111111111111111111"));

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      elsif run("if doing BLT write then data is placed on data lines") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_WRITE;
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        int_am_i <= c_AM_A24_BLT;
        int_addr <= (others => '1');
        int_data_i <= (others => '1');
        
        wait for 20 ns;
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        check_equal(int_err_code, c_ERR_OK);
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        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        check_equal(vme_data_dir, c_PIN_OUT);
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        check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0));
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      elsif run("if doing BLT write DS* goes high on slave ACK") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_WRITE;
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        int_am_i <= c_AM_A24_BLT;
        int_addr <= (others => '1');
        int_data_i <= (others => '1');
        
        wait for 20 ns;
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        check_equal(int_err_code, c_ERR_OK);
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        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        check_equal(vme_data_dir, c_PIN_OUT);
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        check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0));
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        int_vme_go <= '0';
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        wait for 40 ns;
        check_equal(vme_ds_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"00"));        
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        vme_dtack_n_i <= '0';
        wait for 10 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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      elsif run("if doing BLT write with BLT_STOP then FSM => IDLE") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_WRITE;
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        int_am_i <= c_AM_A24_BLT;
        int_addr <= (others => '1');
        int_data_i <= (others => '1');
        
        wait for 20 ns;
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        check_equal(int_err_code, c_ERR_OK);
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        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        check_equal(vme_data_dir, c_PIN_OUT);
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        check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0));

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        int_vme_go <= '0';
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        int_blt_decided <= '0';
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        wait for 40 ns;
        check_equal(vme_ds_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"00"));        
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        -- Slave ack
        vme_dtack_n_i <= '0';
        wait for 10 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        int_blt_decided <= '1'; int_blt_continue <= '0';
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        wait for 20 ns;
        check_equal(vme_as_n_o, '1');
        check_equal(busy, '0');
        
      elsif run("if doing BLT write with BLT_CONTINUE then new data is placed.") then     
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        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_WRITE;
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        int_am_i <= c_AM_A24_BLT;
        int_addr <= (others => '1');
        int_data_i <= (others => '1');
        
        wait for 20 ns;
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        check_equal(int_err_code, c_ERR_OK);
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        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        check_equal(vme_data_dir, c_PIN_OUT);
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        check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0));
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        int_vme_go <= '0';
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        int_blt_decided <= '0';
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        wait for 40 ns;
        check_equal(vme_ds_n_dir, c_PIN_OUT);
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        check_equal(vme_ds_n_o, unsigned'(B"00"));        
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        -- Slave ack
        vme_dtack_n_i <= '0';
        wait for 10 ns;
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        check_equal(vme_ds_n_o, unsigned'(B"11"));
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        -- Slave rescind
        vme_dtack_n_i <= '1';
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        int_blt_decided <= '1'; int_blt_continue <= '1';
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        int_data_i <= (others => '0');
        int_addr <= (others => '0');
        wait for 10 ns; -- BLT decision
        wait for 10 ns; -- DTACK* detection
        wait for 40 ns; -- D -> DS* delay

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        check_equal(vme_data_o(31 downto 0), int_data_i(31 downto 0));
        check_equal(vme_ds_n_o, unsigned'(B"00"));
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      elsif run("if no slave ack is received, then BERR is fired") then     
        
        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_READ;
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        int_am_i <= c_AM_A24_DATA;
        int_addr <= (others => '0');
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        wait for 20 ns;
        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        
        check_equal(vme_as_n_dir, c_PIN_IN);        
        wait for 40 ns;
        check_equal(vme_ds_n_dir, c_PIN_OUT);
        check_equal(vme_ds_n_o, unsigned'(B"00"));

        -- Simulate stuck bus.
        vme_ds_n_i <= "00";       

        wait for 2750 ns;
        check_equal(vme_berr_n_dir, c_PIN_OUT);
        check_equal(vme_berr_n_o, '0');

        check_equal(int_err_code, c_ERR_TIMEOUT);

      elsif run("only exist timeout when strobes are released") then     
        
        vme_dtack_n_i <= '1';
        vme_berr_n_i <= '1';
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        int_vme_write <= c_VME_READ;
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        int_am_i <= c_AM_A24_DATA;
        int_addr <= (others => '0');
        
        wait for 20 ns;
        check_equal(vme_addr_dir, c_PIN_OUT);
        check_equal(vme_am_dir, c_PIN_OUT);
        check_equal(vme_iack_n_dir, c_PIN_OUT);
        check_equal(vme_addr_o, int_addr);
        
        check_equal(vme_as_n_dir, c_PIN_IN);        
        wait for 40 ns;
        check_equal(vme_ds_n_dir, c_PIN_OUT);
        check_equal(vme_ds_n_o, unsigned'(B"00"));

        -- Simulate stuck bus.
        vme_ds_n_i <= "00";       

        wait for 2750 ns;
        check_equal(vme_berr_n_dir, c_PIN_OUT);
        check_equal(vme_berr_n_o, '0');
        check_equal(int_err_code, c_ERR_TIMEOUT);

        -- Release bus
        vme_ds_n_i <= "11";
        wait for 10 ns;
        check_equal(vme_berr_n_o, '0');
        wait for 10 ns;
        check_equal(vme_berr_n_o, '0');
        wait for 10 ns;
        check_equal(vme_berr_n_o, '0');        
        wait for 10 ns;
        check_equal(vme_berr_n_o, '1');        
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      end if;
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    end loop;
    
    test_runner_cleanup(runner); -- Simulation ends here
  end process;

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  clk <= not clk after 5 ns;
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  test_runner_watchdog(runner, 5000 ns);
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  dut : entity work.vme_data_bus
    generic map (
      CLOCK_PERIOD => 10
      )
    port map (
      clk => clk,

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      vme_addr_i => vme_addr_i,
      vme_addr_o => vme_addr_o,
      vme_addr_dir => vme_addr_dir,
      vme_addr_oe_n => vme_addr_oe_n,
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      vme_am_i => vme_am_i,
      vme_am_o => vme_am_o,
      vme_am_dir => vme_am_dir,
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--    signal vme_am_oe_n	: std_logic -- Shared with addr
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      vme_write_n_i => vme_write_n_i,
      vme_write_n_o => vme_write_n_o,
      -- write shares DIR and OE with AM

      vme_data_i => vme_data_i,
      vme_data_o => vme_data_o,
      vme_data_dir => vme_data_dir,
      vme_data_oe_n => vme_data_oe_n,

      vme_as_n_i => vme_as_n_i,
      vme_as_n_o => vme_as_n_o,
      vme_as_n_dir => vme_as_n_dir,

      vme_iack_n_i => vme_iack_n_i,
      vme_iack_n_o => vme_iack_n_o,
      vme_iack_n_dir => vme_iack_n_dir,

      -- Always enabled, always input
      vme_iackin_n => vme_iackin_n,

      -- Enable IACKOUT_n. Will be pulled low 
      vme_iackout_n_oe_n => vme_iackout_n_oe_n,    

      vme_dtack_n_i => vme_dtack_n_i,
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--      vme_dtack_n_o => vme_dtack_n_o,
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      vme_dtack_n_dir => vme_dtack_n_dir,

      vme_ds_n_i => vme_ds_n_i,
      vme_ds_n_o => vme_ds_n_o,
      vme_ds_n_dir => vme_ds_n_dir,

      vme_berr_n_i => vme_berr_n_i,
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      vme_berr_n_o => vme_berr_n_o,
      vme_berr_n_dir => vme_berr_n_dir,
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      -- Request bus
      vme_br_n_o => vme_br_n_o,
      -- Receive bus grant
      vme_bgin_n_i => vme_bgin_n_i,
      -- Output bus grant
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--      vme_bgout_n_o => vme_bgout_n_o,
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      -- Signal bus ownership
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--      vme_bbsy_n_o => vme_bbsy_n_o,
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      -- Signal the we should clear bus
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      vme_bclr_n_i => vme_bclr_n_i,
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      busy => busy,
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      int_addr => int_addr,
      int_data_i => int_data_i,
      int_data_o => int_data_o,
      int_am_i => int_am_i,
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      int_vme_write => int_vme_write,
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      int_vme_go => int_vme_go,      
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      int_err_code => int_err_code,
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      int_data_strobe => int_data_strobe,
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      int_blt_decided => int_blt_decided,
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      int_blt_continue => int_blt_continue,

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      int_timeout_n    => '1'
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      );
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end architecture;